Does the nRF52832 (nRF52 DK) have the DWT_CYCCNT cycle counter register?

[jp_is_my_name]

In IAR  it shows the cycle count registers and they appear to work as expected  in that view (shown as CYCLECOUNTER) . In  the IAR Project/SFRSetup  it shows the address of DWT_CYCCNT as 0xE0001004; however if  I read from that address in C code or view that memory location in IAR  the value (or values at nearby addresses) do not match what is shown in the IAR register window and the value read is garbage.  It seems like if the register is supported, that this address is wrong.  I didn't see the register in the processor data sheet, but it may be listed using a different string so the search didn't work. Note I'm building a Hello World bare-bones app and am not including the NRF SDK.

E.g. I expect this function to work (correspond to what is shown in IAR).

#define get_timer()   *((volatile unsigned long*)0xE0001004) 

[jp_is_my_name]

Answering my own question: Yes the chip does have a functioning CYCCNT register located at that 0xe0001004 address.

It turns out when "ETM Trace" is enabled in IAR, the DWT_CYCCNT does not work as expected (perhaps someone else can explain why). The issue is fixed when ETM Trace is disabled. Also while trying to figure out what the issue was I looked at the Nordic SDK function   NRF SDK nrfx_clock_anomaly_132()  as a reference. This function does 2  additional initialization operations to enable the cycle counting. I found that these 2 operations are not required for a bare-bones IAR app, but they may be required in other applications.

*((volatile unsigned long *)0xE000EDF0UL) |= (1UL << 24);  // CORE_DEBUG, enable

*((volatile unsigned long*)0xE0001000UL) |= 0x00000001UL;   //CYCCNT enable