Power consumption in RESET state for a solar powered device

[Thomas N.]

Dear Nordic Team,

We are currently evaluating the nRF52832 / nRF52810 for our product, a solar powered wearable designed as part of a safety system in the sailing sport. Minimal power consumption is critical to us as a small solar cell buffered by super capacitors is our sole energy supply.

We are currently performing some tests with the nRF52 DK pc10040. During these tests we figured out, that the nRF52 draws about 440µA when the Reset Pin 21 is pulled low. This would be a show stopper for the nRF52 chip for our use-case, as the solar cell (and the eventually discharged super capacitors) might not be able to deliver such "high" currents. This would prevent the solar cells to charge the super capacitors to a voltage where the nRF52 could start working properly. We have a micro-power battery management system which would release the reset pin when VDD is higher than 1.8V.

My questions:

1. Can you confirm the 440µA drawn by the nRF52832 in the nRF52 DK, when reset pin 21 is enabled and pulled low?
2. If 1. is a yes: Can you recommend a procedure of how to prevent the nRF52 chip from drawing "high" currents while the reset pin is pulled low? 

Thanks in advance and best regards,
    Thomas

[Kenneth]

Hi,

That is likely correct, for instance there is a internal pull up of around 13kohm, this will draw about 200uA. In addition most internal regulators are powered keeping the chip in reset state, which is another 200uA (if not more). Reset state is not a low power mode, so there is no way to avoid this current consumption.

Best regards,
Kenneth