Minimum Decoupling caps

[vkbakken]

Dear support,

What are the absolute minimum decoupling cap sizes running the nrf52810? The application is extremely power sensitive and it is not desirable to have any larger CAPs than strictly required. Bigger the CAP the more leakage - and that is simply not desirable - also the bigger the CAPs the more inrush when turning on. The device runs in LDO mode - as there is no gain from using the DC/DC since sleep vs on cycle is tiny.

Thanks,

-V

[Andreas]

Hi V,

 

The IC is designed and characterized to operate with 100 nF decoupling caps on each VDD pin, we can as you might understand not guarantee that decoupling smaller than this is sure to not cause any issues. Considering the specification is 100nF +/- 10% you would still be inside spec with e.g. 82 nF +/- 2%, not sure if this yields enough improvement to be worth the hassle.

 

Decoupling capacitors on DEC pins shall be the specified capacitance and rating.

 

Best regards,

Andreas

[vkbakken]

Andreas,

Let us look at the QFAA and CAAA versions of the nRF52810. This is the same die just different packaging. However decoupling is different as QFAA version has one more VDD pair and the CAAA is missing DEC3 (That is recommended on QFAA).

So I have some follow-up questions:

1. VDD caps are sized for a specific inrush current. This should be the same on both packages - so why add a second 100nF?

2. DEC4 is it 1uF. Is this for the LDO to be stable? Or is it sized for an internal load of X in peak? For instance in ULP mode the smallest CAP (With least leakage) would be desirable. If this is sized for writing flash for instance what would it be if flash write was not to be supported?

3. DEC1 is 100nF for 0V9 digital supply. This CAP must be sized for some maximum load of digital content in the design. What would it be in an application specific scenario where CPU+1block of RAM+ADC is used?

4. Application used a 3V battery so PSRR is pretty much as good as it gets - how does that impact CAP sizing....if they are there for filtering at all...

-Vemund

[Andreas]

Hi,

 

1 and 4 I will need input from the designers to provide a confident answer, I will get back to you.

 

As for 2 and 3 the respective capacitances which the regulators are verified stable and operating according to spec for. We do not allow changing these and from experience boards with incorrect caps on the DEC pins tend to not work. I will run this by the designers also but I expect the answer will remain the same, you are not the first one to ask about this.

 

Best regards,

Andreas

[vkbakken]

Andreas - appreciate you taking it for a good looksie. Looking forward to your reply.

[vkbakken]

Was there a response to 1+4?

[Andreas]

Hi,

 

Unfortunately we are a little reluctant to approving anything but what we have verified internally. Regulators have been dimensioned to the decoupling in the reference schematic, and this is what we verify, diverging from this can cause unpredictable behaviour and worst case an unstable power supply, as I said before.

There is a gradual risk increase as you deviate from the reference schematic though, so you can probably deviate a bit on your own risk if you test and verify well on your end. You mentioned the fact that there is 2x 100nF on the WLCSP part, compared to 3x 100nF on the QFN part - removing the one 100nF on the QFN part should thus probably not cause any issues as long as you do not need it there for filtering.

 

Best regards,

Andreas