Setting the SCLK of my SPI master

[Keven]

Hi, 

Sorry if my english isn't perfect but I have a quick question and I could't find a good answer for what I'm looking for. I'm using a FPGA Arty S7 as a SPI master and a nRF52840 as a SPI slave. I want to know if I can set my master SCLK as a value that isn't in the bank of the nRF52840 SPI (125k, 250k, ... 8mbps).

Since my SPI master is working on a 100MHz clock and I can only work with a clk_div as an integer for dividing the clock of the FPGA for my SCLK, I can't set a good value for 4MHz or 8mHz. For my project, I want to have the fastest I can get (closest to 8MHz). I tried to set my master with a clk_div of 8 which technically should get me a SCLK of 6.25MHz but it doesn't seem to work since I'm getting wrong data. When I set my clk_div to 25, I get a good 2MHz which make everything working fine and I get good data.

Thank you for your answer,

Keven

[Øyvind]

Hello Keven, 

Please correct me if I'm wrong, but isn't 100MHz/25 = 4 MHz? Are you running 50MHz? This more correct with regards to the numbers you are mentioning: 50MHz/8 = 6.25 and 50MHz/25=2MHz.

Kind regards,
Øyvind

[Keven]

The formula I'm using is this one :

It's using the clock of my FPGA and divide it by 2 times the clk_div which make things more complicated for me. I should have put that formula in the first place to avoid misunderstanding.

Thank you for your reply,

Keven