Setting the SCLK of my SPI master

[Keven]

Hi, 

Sorry if my english isn't perfect but I have a quick question and I could't find a good answer for what I'm looking for. I'm using a FPGA Arty S7 as a SPI master and a nRF52840 as a SPI slave. I want to know if I can set my master SCLK as a value that isn't in the bank of the nRF52840 SPI (125k, 250k, ... 8mbps).

Since my SPI master is working on a 100MHz clock and I can only work with a clk_div as an integer for dividing the clock of the FPGA for my SCLK, I can't set a good value for 4MHz or 8mHz. For my project, I want to have the fastest I can get (closest to 8MHz). I tried to set my master with a clk_div of 8 which technically should get me a SCLK of 6.25MHz but it doesn't seem to work since I'm getting wrong data. When I set my clk_div to 25, I get a good 2MHz which make everything working fine and I get good data.

Thank you for your answer,

Keven

[awneil]

Keven said:

SCLK as a value that isn't in the bank of the nRF52840 SPI (125k, 250k, ... 8mbps)

Surely, they only apply when the nRF is generating the clock; ie, when the nRF is Master?

If the nRF is the slave, then it receives its clock from the Master; it doesn't have to generate it, so isn't constrained by that list.

The only constraint would be that you don't exceed the maximum clock which the nRF can accept.

[Keven]

I tried to plug in the 6.25MHz from my SPI master and the data I received was wrong. Maybe I'm doing something wrong and the data should be right like you said. I'm going to take another look on that.

Thank you for your reply.

Keven

[awneil]

Keven said:

the data I received was wrong

In what way(s) "wrong" ?

Have you checked with an oscilloscope that the waveforms are all OK?

Do you have the correct SPI Mode?

[Keven]

Yeah I'm pretty sure I did setup everything fine (CPOL, CPHA are the same on both sides). I'm using the J-link RTT Viewer with the NRF_LOG_HEXDUMP_INFO function to be able to see the bytes I'm receiving. The oscilloscope confirms it. For example, I'm receiving 4F on the first byte instead of 4E.