CPU memory accesses interfering with radio DMA

[abs]

Hi there,

I am working with the NRF52840 Dongle and have been trying to verify what sort of influence other processes on the chip could have on the radio. Specifically, I was wondering whether having the CPU write to or read from memory during rampup of the radio or transmission of a packet would have any impact on the timing or even cause the transmission to fail.

From the NRF52840 Product Specification I gathered that this should theoretically be possible, since the CPU has a higher AHB priority than the radio, provided

• the CPU is accessing the same RAM slave as the radio
• the CPU is generating enough traffic to cause congestion (filling the 32-bit bus width all the time?)

I have tried to generate this sort of traffic by reading from and writing to the same RAM slave as the PACKETPTR points to a large number of times just before and during an ongoing transmission. However, this did not seem to have any impact on the transmission. My assumption would be that this simple setup does not work due to the way instructions are processed and bus accesses are handled. However, I am not too familiar with the low level details of these processes on the chip.

So, my question is: Is it possible to generate enough bus traffic using just the CPU to interfere with the radio? If so, under which circumstances?

Thanks for your time!

[Dmitry]

Hi,

even at 2 Mbps, you'll receive or transmit one byte every 4 usec, that is 256 CPU cycles. To lock bus entirely, I imagine 32 consecutive STM/LDM {r0-r7} instructions...  If you turn on direction finding (on nRF52811), you'll get much higher RAM traffic caused by radio - 4 bytes every 0.125 usec, and I didn't encounter any congestions even in this case. 

[abs]

That makes sense, thanks!