TWI Max Drive (Sink) Current

[Bob]

In "nRF51 Series Reference Manual", in TWI chapter, it is mentioned to configure the GPIO pins with drive strength S0D1, to secure correct signal levels on the pins used by the TWI master when the system is in OFF mode, and when the TWI master is disabled

In " Product Specification", in TWI specifications chapter, the max sink current for a pin configured as SCL or SDA is not specified when TWI master is active. 

What is the max sink current for both TWI pins? 

Same as standard drive (0.5 mA)?

Same as high-drive (5mA)?

Both 7.5mA (Max. number of pins with 5 mA high drive is 3 = 15mA, so 15mA / 2)?

Other value's ( I2C reference manual)?

Thanks
  

[Jørgen Holmefjord]

Hi,

If nothing else is configured, the pins are standard drive.

Best regards,
Jørgen

[Bob]

Hi,

To be sure, we can configure the pins as H0D1 when TWI is enabled to get the 5mA sink current for TWI and SDA, right?

When TWI is disabled or system in OFF mode, is switching back really necessary to S0D1? Or does H0D1 performs as well as S0D1 in TWI disabled or system in OFF. 

I can understand the other modes will influence the I2C signal, but I don't understand why H0 instead of S0 will influence the signal, cause the high level is still disconnected (D1). Is there an explanation for it?

[Jørgen Holmefjord]

Bob said:

To be sure, we can configure the pins as H0D1 when TWI is enabled to get the 5mA sink current for TWI and SDA, right?

Yes, the drive and pull settings should still be configurable when pins are used for TWI peripheral. 

Bob said:

When TWI is disabled or system in OFF mode, is switching back really necessary to S0D1? Or does H0D1 performs as well as S0D1 in TWI disabled or system in OFF. 

Yes, H0D1 should work as well. S0D1 is the default and is most likely why this is specified in the table.