SPI + GPIOTE + UART

[norbe13]

Hello Everyone,

I'm currently developing a SoC and I would like to achieve a correct interaction between the SoC and the Nordic Nrf52832.

The output of the SoC is a PISO register (Parallel Input to Serial Output). The 8 bits data reach the register at 200 kHz (1MBps). The idea is to transfer this data to a computer through the Nordic Nrf52832, by:

-A flag (an output signal of the SoC), enables a GPIOTE event at the Nrf52832 each time the data is ready.

-This event, through PPI, enables the SPI protocol of the Nrf52832. The SPI protocol enables de SPI_CLK, that is connected to the PISO register. The 8 bites data is transfered to the Nrf52832 at a high rate (for example, 4 MBps) and saved into a buffer.

-This buffer, through PPI, transfers this data to the UART, and the UART send the data to a PC.

This should take place every time the flag is high, I mean, : flag -> GPIOTE -> PPI -> SPI (ENABLE) -> 8 serial bits from SoC to NRF -> Buffer at NRF -> PPI --> UART ... WAIT FOR THE NEXT FLAG.. 

In conclusion, the whole operation has to be faster than 200kHz to avoid data loss.

My questions are the following one:

i) Do you believe that it is possible? (Due to the high rates of transmission)

ii) Do you think that there is an easier way to transmit the data?

iii) I'm doing in that way because I don't find a way to overcome the problem that if the PISO is changing its value and it the SPI_CLK is enabled, there will be an error in the tramsmited data.

Thank you

[ovrebekk]

Hi

I am a bit confused by your data throughput estimate. Wouldn't 8-bit every 200kHz correspond to a throughput of 1.6Mps?

i) Whether the throughput is 1Mbps or 1.6Mbps it is still too much for the UART to handle. The max UART baudrate is 1Mbaud, and at minimum one ninth of that baudrate is lost by having to send a stop bit for every byte. 

It should be possible to make the SPI fire once every 5us, but it is not trivial in master mode. You probably need to use the ArrayList feature to avoid having to set up the RAM buffers from the CPU at every 5us interval. 

ii) It would be considerably easier if the SoC were to operate as the master, sending clock and chip select in addition to the data. Then you could set the nRF52832 in SPI slave mode, and have it buffer data in multi byte sized packets that you can process in bulk at a much slower rate. 

iii) Are you able to double buffer the PISO value?
Then it should be easier to ensure safe handover between the SoC and the nRF. 

Best regards
Torbjørn