How much is the expected time period from the time VDD goes above 1.75V to main()? I am using a custom bootloader and am seeing a ~4.5s (yes seconds!) delay in getting to bootloader main(). When the debugger is connected this time is in the 100s of ms, which is what I would expect without the bootloader on first power up (1.8V VDD rail starting up). Here's a scope shot of my 1.8V rail (CH2) starting up and the IO (CH1) toggling (one of the first things done inside main()). Any help is greatly appreciated.
Do you see the same problem if you are using VDD = 2.0V?
Is this measured close to the VDD pin?
What is the content of UICR after power up? Type: 'nrfjprog --readuicr dump_uicr.hex'
Any schematic to share?
I can not try with 2V because this is in a system powered with a 1.8V regulator. As seen in my scope shot the bus looks clean.
I checked the UICR after power-up most locations are FFs except for some of the 'reserved for Nordic firmware design' locations below:
Does this tell you anything? Where else could I be looking to debug this issue?
I am using a BMD-340 module.
The only explanation I have is that something is charging up, e.g. that even if you supply 1.8V, you have some series resistor/diode that limit the current going to the nRF52840 thereby keep it in some kind of reset state. That is why I wanted you try to tweak up the VDD voltage a bit to see what happens. I assume you are not able to open the module to find the exact chip markings?
These modules are using nrF52840-QIAA production release 1 silicon. BMD-340 doesn't have anything that would slow the VCC down by 3-4 secs.
I am sure I am missing something somewhere. Could there be something in the boot-up process that may cause a long delay? Although as I mentioned earlier if I use the debugger and run the bootloader project, I do not see this huge a delay.