high data rate communication with SPI ADC

[Dopler]

Hello.
We have product based on NRF51822 chip. 24 bit 4 channel ADC connected through SPI to MCU. Data rate is 250 Hz (4 ms). We send two ADC samples evry notification packet. In first realysation ADC was SPI slave, MCU was SPI Master. ADC generate DATA READY event on pin, MCU in interrupt initiate data transfer. Becouse MCU can be busy in SoftDevice routins for 6 ms, some samples were missing.
With some effort i made programm in which ADC and MCU were SPI Slave and SCK and CS were genereted by PWM (using gpiote and PPI).
But now we are developing new product with 6 channel ADC and data rate 1000 Hz. We no need send all data by BLE, but we can not miss any samles. Is it possible to solve this problem using a NRF52 mcu without using the described tweaks?

[Jørgen Holmefjord]

Hi,

The SAADC peripheral in nRF52 series ICs support EasyDMA for sampling directly to RAM buffer. By using PPI to trigger the samples, this can be done completely without CPU intervention. The SAADC peripheral also supports double buffering, allowing you to process one buffer while sampling is done to another buffer. 

[EDIT]: If you are still planning to use an external ADC, the SPIM peripheral also support EasyDMA. The DATA_READY pin from ADC can trigger the SPI transfer task directly using GPIOTE and PPI.

Best regards,
Jørgen

[Jørgen Holmefjord]

Resetting the pointer will have to be done in software. There is no mechanism in hardware to reduce the buffer pointer. 

[Dopler]

How can this be done safely?