Hi,
pstorage_raw_store() API fails as p_src address is not 4 byte aligned (i.e. 0x20002b1a), as p_src is RAM address and also as its "SOURCE" address is it necessary to be 4 byte aligned?.
Thanks Manju
Hi,
pstorage_raw_store() API fails as p_src address is not 4 byte aligned (i.e. 0x20002b1a), as p_src is RAM address and also as its "SOURCE" address is it necessary to be 4 byte aligned?.
Thanks Manju
The ARM Cortex M0 which the nRF51822 is based does not support mis-aligned memory access. It will hard fault if a non 32 bit access is attempted. So it is better that the pstorage code check the alignment and return an error instead of allowing the fault.
See this section of the ARM M0 manual: Memory access
Hi,
GCC gives it 4-byte aligned but Keil is not, so I am planning to use force alignment like below
static uint8_t data[20]attribute((aligned(4)));
is it the only way to go?
Thanks Manju
Hi,
GCC gives it 4-byte aligned but Keil is not, so I am planning to use force alignment like below
static uint8_t data[20]attribute((aligned(4)));
is it the only way to go?
Thanks Manju