nRF9160 Input Leakage Current Spec

[Colby]

Howdy,

Part of our design process for trying to achieve the most time out of the product's battery is optimizing any pull-up and pull-down values such that when active there is not "wasted" current.

An easy way of getting a quick estimate on the maximum resistance we can use is typically done by the following steps:

• Obtaining the minimum voltage input threshold for a logic high (Vih)
• Subtract the Vih spec from the largest VDD value (voltage being pulled up to) to get the voltage drop across the resistor
• Divide the resistor's "worst case" voltage drop by the the Input leakage current spec on a digital pin

So a hypothetical example: maximum VDD of 4.2V (fully charged LiPo), Vih of 2.2V when VDD >= 4.0V, input leakage spec of 1uA. This example results in a "worst case" 2V drop across a resistor that needs just over 1uA of current going through it. 2V/1uA = 2 MOhm resistor (but with wanting to provide some buffer for specs and needed to be just over 1uA we bump this down to maybe 1 MOhm or 1.5 MOhm.

Point here is, without a spec on the input leakage, there is no way to know just how much we can push the resistance values to minimize our current drain. We have not found any spec provided in the product specification or elsewhere on the DevZone of the nRF9160's input current leakage or input resistance which would help us in this matter. We would very much appreciate getting some advice or direction on this information.

Note: This is more specifically pointed at pins configured as digital inputs

Thank you for your time.

V/R,

Colby

[Håkon Alseth]

Hi,

 

Input resistance of a GPIO (without PULL configured) is not specified in the PS, but I can tell you that it will be high (high MOhm area). As an example, our sleep numbers are measured on target, with any potential leakage on all GPIOs included;

https://infocenter.nordicsemi.com/topic/ps_nrf9160/_tmp/alta.nRF9160/autodita/CURRENT/parameters.id_current_sleep.html?cp=2_0_0_4_1_0_0

 

Kind regards,

Håkon

[Colby]

Howdy Håkon,

Thank you for your reply.

Håkon Alseth said:

As an example, our sleep numbers are measured on target, with any potential leakage on all GPIOs included

I understand and appreciate the numbers shown for sleep currents, and it is important to note,as you say, that any leakage on the GPIOs is also included in the number. That being said, I assume (with a pretty high level of certainty) that all of those GPIO pins were configured as inputs with disconnected input buffers. I'm specifically talking about the PIN_CNF[n] register where the pins were more than likely configured as inputs (DIR bit) and then set as disconnected (INPUT bit), with no pull (PULL bits).

The above makes the most sense in terms of achieving those sleep numbers, and from a marketing perspective it makes complete sense and is expected. In fact, if someone IS pursuing the lowest power consumption possible then looking at the most ideal, low current situation possible is definitely part of the information they can use in part selection. It is not, however, the only piece of information needed. In almost any low power application it will be necessary for at least some inputs to be configured with the input buffers connected so the processor has interrupts/wake-up signals. With a pursuit of those ideal sleep numbers, hardware designers need the input leakage current/input resistance specs in order to dial in the optimal external components on the circuits into these interrupt/wake pins.

Håkon Alseth said:

Input resistance of a GPIO (without PULL configured) is not specified in the PS, but I can tell you that it will be high (high MOhm area)

Can you be a little more clear with this estimate? I am unsure if you are implying that the resistance is going to be in the 700+ MOhm or if you mean 7-10 MOhm, etc. The difference in input leakage from 5 MOhm to 500 MOhm is a large amount, and this would be affecting every interrupt pin we have.

Thank you again for your time and efforts,

V/R,

Colby

[Håkon Alseth]

Hi Colby,

 

I got feedback from R&D, and the input resistance on a GPIO configured as input would be >> 50 MOhm. As we do not have a full characterization, I am being restrictive on the measured numbers, as they are not characterized fully over the full working temp / voltage and so-forth.

 

Kind regards,

Håkon

[Colby]

Howdy Håkon,

That information should be decent enough for us to get in the ballpark. As a note for future improvements, including a spec for this information would be very appreciated in Product Specifications.

Either way, we are happy to have the information you were able to dig up and will use it as best we can. Thank you for your help!

V/R,

Colby