nRF52840 VDDH Decoupling Capacitors (C19, C21)

[Michael]

I read the NWP-030 White Paper, Power Supply Decoupling Capacitor Selection and focused on the nRF52840 Sections. The document did not go into [Min - Typ - Max] Effective Capacitance values for the VDDH Capacitors, C19 and C21. I'm guessing the reason is the first of the two power stage setup depicted in [Figure 5] of the document allows more variability in the first stage. The nRF52840_qiaa reference schematic has 4.7uF decoupling capacitors for both C19 and C21. Is this value recommended if these two X7R capacitors will be biased at 5V?

I am dual powering my chip in High Voltage Mode with USB Power going into VBUS and a Li-ion battery charger circuit based on the Thingy52 (input also from USB) boosting battery voltage to 5V. As the only supply into the chip, I thought capacitance needs here would be higher. What effective capacitance should I aim for at these two pins?

[Andreas]

Hi,

 

C19=4.7µF is referenced to 5V yes. This you can choose slightly larger though if you want. 

From what I understand your planned configuration sounds like config.2 or 5 of the reference designs, USB to the USB peripheral and a battery charger, which in turn powers VDDH. I would replicate the reference design, i.e. 4.7µF on VDDH, VBUS and 4.7µF+1.0µF+3x100nF on VDD as this is the design that is verified on our end.

 

Best regards,

Andreas

[Michael]

It is a mix between Configs 1 and 2 although I am trying to decide if I need a 4.7uF capacitor at VBUS like config 2. I am copying the Thingy52 example of having a 10uF and 100nF capacitor near the micro-USB-B but I feel like I need a capacitor close to the VBUS pin, maybe I am wrong about that.

I was planning on mostly following the design other than small things such as not adding traces for the Not Connected C10 and C13. The one issue I'm having is capacitance loss due to DC bias. I was originally planning on setting REG0 to 3.0V since that is the voltage I will be programming the chip at. However, at that voltage I need to increase my decoupling capacitors since I am expecting a 60% drop in capacitance at 3.0V. But I am wary of doing this since I've had success in the past following the reference designs. 

After thinking this through, REG0 is only applicable in High Voltage Mode so I should still be able to set my REG0 value to 2.4V for operation but program the chip at 3.0V through VDD in Normal Mode. This will still allow my circuit to function but should put me within the capacitance range for VDD decoupling. The one change I will have to make from the reference circuit is increasing the capacitance of C20, since at 3.3V the effective capacitance of my 4.7uF capacitor is below 2.35uF. The thing that is confusing me the most is the capacitor I chose is the one Nordic chose for it's 4.7uF, Samsung's CL10B475KQ8NQNC. Which according to the datasheet should have a 60% capacitance drop. Is there something I'm missing here?

[Andreas]

Hi,

 

See instead Thingy:91(HW files in the download section), that uses nRF52840 and has a similar USB interface as you plan, both a charger and USB interface on nRF52840. Even though we have the 4.7µF on the VBUS pin on nRF52840, but I do not believe that should be needed if there is sufficient capacitance otherwise on the net, and it is fairly compact. You might want to at least get the mounting pads in there (either 4.7µF or 100nF) in case something is acting up. We have only verified the device with the cap in place, so we can not give any guarantees that this will work though.

CL10B475KQ8NQNC is the one we have been using in our verification tests and reference designs, meaning it should be fine. I am not able to find any mention of the 60% drop in the datasheet though? 

 

Best regards,

Andreas

[Michael]

The spec sheet I found for that Samsung capacitor did now show it's DC bias but it did have the DC bias of a 10uF, 6.3V cap in the same family. For that cap, it showed a 60% drop at 3.3V.

However, I have had success in the past with Nordic reference designs so I will be following the reference design's values for all capacitors by having 4.7uF capacitors placed at VDDH and VBUS like Thingy91 and reference design #2 for my initial design. Thank you for your help Andreas.