Dear nRF52832 experts,
I have a SPI slave device which can periodically notify the MCU with data ready (DRDY) signal. For each DRDY signal, we should perform a SPI transaction to read a sample of less than 30 bytes into RAM buffer. The process will repeat periodically (from 200Hz to 8Khz) when the slave device is in continuous collection status.
I am wondering if we can manage the DRDY and sample reading without troubling the CPU until the sample is in RAM? if it is possible, then can we further to notify CPU once only after N samples are in RAM?
The raw idea I am thinking is to have below triggering chain: GPIOTE --> SPIM --> COUNTER --> CPU, since I am very new to nRF52, I am still unsure if the chain is feasible? If yes how to set it up?
The SPIM peripheral will by default transfer data to/from RAM and give you an event once the entire transfer is completed. It is possible to enable events at end of TX and RX operations alone as well, but these are not used by the SPI master driver. Performing multiple consecutive transfers without CPU intervention requires use of EasyDMA ArrayList feature. Support for this is implemented in the SPI master driver for SPIM peripheral by using the flags described on the linked page. This page also includes a code sample for exactly what you are requesting.
If you want to get an interrupt only after a certain number of samples, the END event needs to be connected to a TIMER in COUNT mode.
For SPI master it should not make much difference if you use the legacy driver API or the new nrfx API. There is no performance difference, but using nrfx may simplify debugging a bit since you do not need to go through the legacy layer. Both alternatives use the nrfx driver in the lower levels.
So in my case, I want use s112 with above mentioned SPIM (with GPIOTE/TIMER via PPI), plus console port logging during development phase, can I still take the "nrfx" API approach?
Yet another question: given the SPIM has been set to use array list to read samples, once the last sample buffer was filled by SPIM, upon the next SPIM START task, will it restart from the first sample buffer? If yes, this means that we don't have to change SPIM settings in the counter event handler.
Yes, any peripheral driver apart from the ones mentioned under "migration not possible" in the nrfx migration guide can be migrated to nrfx drivers. It is possible to mix legacy and nrfx drivers for separate peripherals.
As far as I know, the value in the PTR register will be incremented during transfers, and this will not be reset to its original value by itself. If you were to start the transfer again, it would start in the last buffer of the array list and increment from this point. You will have to reset the buffer pointer in SW before starting a new transfer.
Thank you a lot for the explanations. I will close this ticket.