Sample Code for the nrf53

[AMarch]

So the nrf53 codebase is pretty much non-existent from what I can see. Is there any example code to launch the proprietary Enhanced Shockburst in receive mode?

Kind of like to manage a some devices on the application side while packets are flying on the communications side.

Are there any examples of semaphore usage between the two CPUs?

Can you load current nrf52 compiled pieces into each CPU separately and roll your own shared memory manager?

Tony

[Øyvind]

Hello, 

So the nrf53 codebase is pretty much non-existent from what I can see. Is there any example code to launch the proprietary Enhanced Shockburst in receive mode?

 There is currently no example code other than what is available in "Samples and Applications". This is still work-in-progress. In the mean-time, you could have a look at Enhanced Shockburst documentation and sample (nRF5x).

Please see Working with nRF5340 for more information.

Are there any examples of semaphore usage between the two CPUs?

Can you load current nrf52 compiled pieces into each CPU separately and roll your own shared memory manager?

I do not have any answers to this at this moment, will ask our nRF5340 team.

 
Kind regards,
Øyvind

[AMarch]

I noticed there is only one target, is there a way to just target one CPU at a time? I kind of assumed you would be able to load the flash on one , then the other and then let them run. 
Thanks for the links.

[Marciano-PL]

Yes, it is possible to flash on only one core at a time. When you build your application you must decide whether you are building for the APP or NET CPU which will determine which portion of the board you are flashing.

When you connect via nrfjprog or JLink you must specify which core you are addressing.

nrfjprog

nrfjprog -f NRF53 --coprocessor CP_APPLICATION <<insert your options here>>

JLink

J-Link>connect
Please specify device / core. <Default>: NRF5340_XXAA_NET
Type '?' for selection dialog
Device> NRF5340_XXAA_APP
Please specify target interface:
  J) JTAG (Default)
  S) SWD
  T) cJTAG
TIF>SWD
Specify target interface speed [kHz]. <Default>: 4000 kHz
Speed>4000
Device "NRF5340_XXAA_APP" selected.


Connecting to target via SWD
Found SW-DP with ID 0x6BA02477
Scanning AP map to find all available APs
AP[4]: Stopped AP scan as end of AP map has been reached
AP[0]: AHB-AP (IDR: 0x84770001)
AP[1]: AHB-AP (IDR: 0x84770001)
AP[2]: JTAG-AP (IDR: 0x12880000)
AP[3]: JTAG-AP (IDR: 0x12880000)
Iterating through AP map to find AHB-AP to use
AP[0]: Core found
AP[0]: AHB-AP ROM base: 0xE00FF000
CPUID register: 0x410FD214. Implementer code: 0x41 (ARM)
Found Cortex-M33 r0p4, Little endian.
FPUnit: 8 code (BP) slots and 0 literal slots
Security extension: implemented
Secure debug: enabled
CoreSight components:
ROMTbl[0] @ E00FF000
ROMTbl[0][0]: E000E000, CID: B105900D, PID: 000BBD21 Cortex-M33
ROMTbl[0][1]: E0001000, CID: B105900D, PID: 000BBD21 DWT
ROMTbl[0][2]: E0002000, CID: B105900D, PID: 000BBD21 FPB
ROMTbl[0][3]: E0000000, CID: B105900D, PID: 000BBD21 ITM
ROMTbl[0][5]: E0041000, CID: B105900D, PID: 002BBD21 ETM
ROMTbl[0][6]: E0042000, CID: B105900D, PID: 000BBD21 CTI
Cortex-M33 identified.

[AMarch]

Ok thats good information. So theoretically, I could develop two nrf52 type applications and load them into the cores, then talk back and forth through a shared memory block? This would be with the assumption that the cstartup code is identical, which would be rather lucky coincidence.

Also, I am assuming there a build settings for the fixing up the memory offsets depending on which CPU you are on, but maybe locally to each CPU the flash block sits at the same location.

[Marciano-PL]

Yes, applications similar to nrf52. They have different specs though. There is a communication channel which you can use, or DPPI for triggering events across cores.

As for the memory locations, zephyr has the memory regions defined in their board.dts files for the nrf53.