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High Sample Rate with ADC and SoftDevice

Chris

I am trying to sample the ADC every 2ms. I notice lots of slowness with BLE advertising and typically can't connect to device over BLE when sampling. I am using PPI, configuring, and starting before the softdevice is enabled.

  1. Should nRF51822 be capable of reading ADC every 1ms to 2ms reliably?

  2. Should I move all the PPI configuration to after the softdevice is enabled and be using the sd_ppi functions?

Thanks!

Edit: Headline, format, added tags.

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  • 0

    I note that it is not possible to use the ARM core to 'sample' the ADC value regularly enough, BUT Is it possible to use the EasyDMA in the SPIS devices?

    My proposal:

    The ADC would be set to capture a value using the PPI and its START task and a timer, this gives the regular sample, but not the ability to 'save' the value before it is overwritten.

    To 'save' the data, the SPIS could be set to loop back upon itself, with the TXDPTR set to the ADC result address, and the MAXTX set to 1 for 8-bit samples and 2 for 10 or 9 bit samples. The RXDPTR would then be set to a normal RAM address with a normal buffer size for example 256 to capture 256 8-bit samples.

    Then you connect the MOSI and MISO pins, and the SCK to a suitable clock source (maybe the Master's clock, and then finally connect the CSN to a GPIO that is triggered using the PPI to make a suitably long chip enable signal.

    I know this is convoluted, but the SPIS is the only memory bus master other than those used by the SoftDevice. Is this a feasible, if awkward, solution to regular sampling whilst the SoftDevice is enabled?

    It would be useful to have some feedback to this proposal to help me make my product selection as the ADC capability is one of the nRFs key features (aside from its Bluetooth capabilty).

    Yours,

    Peter Myerscough-Jackopson

  • 0 in reply to Peter Myerscough-Jackopson

    The stack generates software interrupts with priority 2 to signal the application of events. So to make a peripheral interrupt handler (e.g. ADC interrupt handler) have higher priority than any BLE callback events you must set the priority of your peripheral interrupt handler to 1 (i.e APP_IRQ_PRIORITY_HIGH). However, when a peripheral interrupt handler has priority APP_IRQ_PRIORITY_HIGH, you can not call any softdevice function from the peripheral interrupt handler, starting with sd_*. You can realize the priority structure in S110 Softdevice Specification v1.2, section 10.2. For nRF51 rev 2, the CPU is blocked during the whole radio event. For nRF51 rev 3, the CPU should be available after each transmitted packet. I expect this to allow 5kHz-10kHz maximum sampling rate for the ADC, but we will have to see what the actual specification for rev 3 reveals.

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  • 0 in reply to Peter Myerscough-Jackopson

    The stack generates software interrupts with priority 2 to signal the application of events. So to make a peripheral interrupt handler (e.g. ADC interrupt handler) have higher priority than any BLE callback events you must set the priority of your peripheral interrupt handler to 1 (i.e APP_IRQ_PRIORITY_HIGH). However, when a peripheral interrupt handler has priority APP_IRQ_PRIORITY_HIGH, you can not call any softdevice function from the peripheral interrupt handler, starting with sd_*. You can realize the priority structure in S110 Softdevice Specification v1.2, section 10.2. For nRF51 rev 2, the CPU is blocked during the whole radio event. For nRF51 rev 3, the CPU should be available after each transmitted packet. I expect this to allow 5kHz-10kHz maximum sampling rate for the ADC, but we will have to see what the actual specification for rev 3 reveals.

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