High Sample Rate with ADC and SoftDevice

[Chris]

I am trying to sample the ADC every 2ms. I notice lots of slowness with BLE advertising and typically can't connect to device over BLE when sampling. I am using PPI, configuring, and starting before the softdevice is enabled.

1. Should nRF51822 be capable of reading ADC every 1ms to 2ms reliably?

2. Should I move all the PPI configuration to after the softdevice is enabled and be using the sd_ppi functions?

Thanks!

Edit: Headline, format, added tags.

[Lucas]

Stefan,

thank you for attempting. It looks like my only options are to wait for REV 3 and hope for the best. Or add a dedicated ADC with built in FIFO into my system, but I really don't want to do that haha.

[Peter Myerscough-Jackopson]

One final attempt at getting regular sampling working could be to use the SPIS for getting the data from the ADC, and then reading the data back into the UART. It looks like the UART can be configured for no parity and hardware flow control OR event based flow control, and it has a FIFO with space for 6 values.

This means that the current limit of one guaranteed sample every 1700 μs (588Hz), is raised to 6 samples in that period(3529Hz), and if the future rev3 doesn't quite make it to 10kHz this method would allow the rate to be multiplied by 6 allowing for 5-10kHz to be easily achieved.

One last attempt......?

[Peter Myerscough-Jackopson]

In retrospect it looks like the UART requires start and stop bits, but the waveforms are not in the pdf.

[Peter Myerscough-Jackopson]

A final comment would be to Stefan. I know Nordic are creating a rev3, but if there is ever a rev4, then a possible idea to enable full utilisation of the ADC using the SPIS loopback method could be achieved if the RESULT register was 'mirrored' / 'repeated' on a contiguous set of addresses. For example if the same RESULT register was accessible at 0x508 and additionally in the range 0x600-0x700, then setting the SPIS to read from 0x600 - 0x700 and controlling the clock as we have been expertimenting with would enable the ADC to be read 40 times without the CPU. It would allow the 50kHz ADC to be controlled by the CPU with a control rate of 1.25kHz. Looking at the NRF_ADC_Type there are actually 700 free register locations in the block after the RESULT register and they could all be set to mirror the RESULT register if desired.

The RESULT register could always be mirrored from 0x508 upwards to a suitable limit, I was just offering a 'the idea as simply as I could.

[Peter Myerscough-Jackopson]

The above idea shouldn't alter the ADC hardware significantly just the address decode for the RESULT register. Given that rev3 should enable 5-10kHz sampling, 5-10 contiguous addesses would enable the ADC to be run at its maximum of 50kHz.