Simultaneous Implementation of buses and UARTS

[javierbio]

Dear Sirs, good afternoon

I am working in a design that includes an nRF52840 as main processor.

I need to know if it is possible to have the following peripherals implemented concurrently:

- SPI Master

- QSPI Master (for flash mem to be used in OTA-DFU )

- I2C Master

- UARTs Qty: 2

Is it possible to share pins between the SPI and QSPI or they have to be implemented as separate instances in different pins?

Best regards,

[Turbo J]

javierbio said:

peripherals implemented concurrently

I see no problems here.

javierbio said:

Is it possible to share pins between the SPI and QSPI

You really don't want to do that - QSPI and SPI are different peripherials on the chip, sharing would require tedious pin re-assignments. The NRF52840 has more than enough pins for separate busses.

[javierbio]

Thanks Turbo for your quick response.

Any pin recommended for QSPI?. Or as stated in other posts pick pins away from radio circutry

Best regards,

[Andreas]

Hi,

 

Yes you should try to avoid the 'low drive, low frequency' ones to avoid affecting the RX sensitivity if there is traffic during RX. Other than that any GPIO can be used, see the pin assignments for the default pins.

 

Best regards,

Andreas