mask FPU IXC exception

[Anthony Ambuehl]

We have an neural network running  on a 52832 using the floating point unit.  We started encountering FPU exceptions so we enabled the FPU IRQ to identify which specific instructions is causing the error.  However we started getting thousands of FPU interrupts caused by the IXC exception, which we do not care about.  Is there anyway to mask which exceptions will actually result in an FPU_IRQ?  The addition of many thousands of interrupts during our processing is slowing our algorithms to the point where the data collection is stalling and overflowing.  

I learned that some processors actually do not connect the IXC bit to the interrupt.  https://www.st.com/content/ccc/resource/technical/document/application_note/10/6b/dc/ea/5b/6e/47/46/DM00047230.pdf/files/DM00047230.pdf/jcr:content/translations/en.DM00047230.pdf

I definitely see the value in not connecting IXC, since this exception occurs very frequently in certain computations.

[Susheel Nuguru]

Hi Anthony,

If you are getting an FPU_IRQ then we can be quite certain that if this is due to IXC then it is connected to the interrupt.

You can confirm that this is the exception flag that is generating the FPU exception if inside the FPU_interrupt there is no other flag set apart from IXC. Unfortunately there does not seem to be any masking of exceptions inside the FPU level. The interrupt can only be masked at NVIC level which will mask other exceptions along with IXC.

[Anthony Ambuehl]

That unfortunately does make the FPU interrupt pretty useless.  I'll leave it disabled during our algorithm processing.  

Is it possible to request additional hardware features for future version of the nrf5* series?  A mask would be really helpful or simply disconnecting IXC as other vendors have done.

[Susheel Nuguru]

Please take a look at nRF53 FPU - Floating point unit (FPU) exceptions. The exceptions can be masked with this new additions of the newer member of the nRF family.