For our nRF52832-QFAA design, we've just completed all tests according EN 300 328 (Radio). All but one test passed: spurious emissions at 4.9 GHz showed -44dBm, exceeding the -47dBm limit.
Our design has a lot of space restrictions, so we could not perfectly copy the reference layout as described here (www.nordicsemi.com/.../nRF52832
Unfortunately, we've also completely overseen both 12pF capacitors, required to short the GPIO pins p0.25 and p0.26 to ground for RF.
In our device, p0.25 and p0.26 are SPI interface lines going over several (small) PCB's via a short flatcable. Mostly unscreened.
During RX spurious radiated emission testing, we saw -44dBm where -47dBm is the limit, at 4.9GHz. No other frequencies were visible.
Our design deviates on the following:
1 - vias underneath nRF: 4 in the corners plus 1. No via close to the RF output.
Reference has 16 in 4x4 pattern
2 - all passive components are on opposite side of the board and have at most a single via to ground nearby. So we have 2 series vias per decoupling capacitor.
Reference has components on same side of nRF and two ground vias very near the decoupling caps. Reference has 0.5 via per decoupling capacitor.
3 - ground plane is far from ideal as a lot of vias create large slits and the board is very narrow.
4- we have several components, like the dcdc conversion inductor, below the nRF chip.
Reference has no components below the nRF chip.
We consider a re-layout in which we will add the 0402 size 12pF capacitors close to the pins and with ground vias close to the caps plus good ground plane.
As this SPI interface is not used now, we even consider not connecting the pins at all if this is safer.
The question is:
- Is the RX spurious likely we've seen originating from p0.25 and p0.26 alone, or are there other source?
- Is it safer to (less emission) to short the pins directly to ground than to use 12pF caps?
- Is the dcdc inductor beneath the nRF acceptable?
- What do we need to do more to be sure about solving the RX spurious emission issue we have seen?
- Will it do to have a 3x3 via pattern underneath the nRF chip?