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GPIOTE IN[n] register description

What exactly are the GPIOTE IN[n] registers?

Is the IN[n] register a function pointer of a function to call when the the input condition occurs on the associated pin?  If so, does this function interrupt the current program execution?

Is it the interrupt handler when a GPIOTE interrupt occurs?

The nRF51 Reference Manual Ch15 GPIOTE Tasks and Events makes no mention exactly what IN[n] is.  It is a 32-bit register, with no register description.  The GPIOTE general description says an event is generated when a rising edge, falling edge or change occurs on a pin associated with a GPIOTE channel.  What exactly is an event?

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  • Thanks Hakon,

    I'm also looking at nRF52 docs as we have replaced the nRF51822 with nRF52832 in one of our products.

    What you said also helped me understand tasks and event in the UART.  It's really quite straightforward.  In the UART tasks are equivalent to configuration register bits in other microprocessors, and events are equivalent to status register flags. I come from a background in PIC24 and STM32, so these task and events threw me initially.

    It would have been great if Nordic had implemented peripherals the same as STMicro in the STM32 Cortex M3/M4.  I guess it's a bit late for that!

    Thanks for your help

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  • Thanks Hakon,

    I'm also looking at nRF52 docs as we have replaced the nRF51822 with nRF52832 in one of our products.

    What you said also helped me understand tasks and event in the UART.  It's really quite straightforward.  In the UART tasks are equivalent to configuration register bits in other microprocessors, and events are equivalent to status register flags. I come from a background in PIC24 and STM32, so these task and events threw me initially.

    It would have been great if Nordic had implemented peripherals the same as STMicro in the STM32 Cortex M3/M4.  I guess it's a bit late for that!

    Thanks for your help

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