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What are the consequences of using low-frequency GPIO lines with a high-frequency signal?

I have an external clock running at 3Mhz which I'd like to align with in software. Consider this contrived example:

// P0.03 is recommended 10kHz or less, but using for 3Mhz
#define CLOCK_PIN NRF_GPIO_PIN_MAP(0,3)

// P0.19 has no specified maximum frequency, and presumably is appropriate
#define CLOCK_PIN_FAST NRF_GPIO_PIN_MAP(0,19)

void init(){
    nrf_gpio_cfg_input(CLOCK_PIN);
}

void align(){
    while(!nrf_gpio_pin_read(CLOCK_PIN){};
    while(nrf_gpio_pin_read(CLOCK_PIN){};
}

void main(){
    init();
    int counter = 0;
    while(counter < 100000){
        align();
        counter++;
    }
}

What would the consequences be of attempting to read values on a GPIO pin not recommended for such a high frequency? Please disregard that a PPI channel and hardware timer would be more appropriate for this contrived example, I would really just like to know any and all consequences for not following the recommended specification for low-frequency GPIO pins.

Thanks!

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  • Hi,

     

    No I probably just mixed up counter and timer when issuing my response to you, sorry about that. Using the HF crystal as source for the HFCLK will give a stable CPU clock, every sample should happen as accurately as possible. I do not believe have investigated whether there can be differences between the pins, the note in the PS only refers to degratation or radio performance parametres.

     

    Best regards,

    Andreas

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