GPIO pull down/up questions

[mcintoda]

1. Is the GPIO pull down/up asserted on the 'inside' of the input disconnect switch or at the input/output pad? The diagrams would indicated that it is on the 'inside' of the disconnect switch.

2. To help mitigate floating inputs, using input disconnect mode should the pull-up/downs be asserted?

3. Are there any bugs known about the GPIO in QFAA ?

[Stefan Birnir Sverrisson]

1-2. I think it should be considered to be as the diagram in figure 15 in the nRF51 Series Reference Manual v3.0 indicates. You anyway only configure a pull when you configure a pin as input. So when you have input you configure pull configuration to avoid pin signal from floating. When you configure a pin as output, your are driving that pin so it will not be floating.

For any GPIO anomalies, look at the PAN documents available on our web site. For anomalies for the most recent nRF51 third revision chip, look at PAN nRF51822 PAN v3.0. For older nRF51 revisions, look at PAN v2.4.

[mcintoda]

The diagram doesn't show if the pull/up down is on the inside (input buffer side) of the input disconnect switch or not. I think what I am observing is that it's on the pad (PCB) side not the input buffer side.