GPIO DIRCLR Register Behavior

[JMJEngineeringConsulting]

Based on nRF52832 datasheet description of DIRCLR register (section 20.3.7), I would expect that writing 1 to bit 8 of that register would set PIN8 (P0.08) to an input pin mode. However, when I do this (write '1' to bit 8 of DIRCLR), after having previously set PIN0 thru PIN7 as outputs using DIRSET register, DIRCLR immediately sets the previously set output pins as inputs. 

Can someone explain my misunderstanding of how DIRCLR register works? 

I am using Segger Embedded Studio v4.52b (Segger compiler & linker) and NRF52 DK board (PCA10040, 2.0.0 2020.10).

Thanks!

[JMJEngineeringConsulting]

My mistake in code. I was doing DIRCLR |= BIT8 instead of DIRCLR = BIT8. So that command was clearing any previously set output pins.