nRF52833 Development Kit Hardware Questions

[cheezballs]

Hi there,

I have a few questions regarding the Development Kit hardware design. I just bought up the polygon pour manager. I noticed that all layers except Mid-Layer 2 are netted to GND. What does ‘VDD_SAM’ allude to in the Mid-Layer 2 polygon pour net? What voltage level does ‘VDD’ refer to in the other Mid-Layer 2 polygon pour net? I have attached images of the Top and Mid-Layer 2 polygon pours:

I see that 'VDD_SAM' is only poured over the area of the interface chip.

I’ve also noticed that there are vias placed all throughout the board, attaching all the ground planes together. Is this advisable in a custom design with four layers? If so, what is the common practice around this (i.e. distance between GND vias)? I have selected one via (circled in orange), and cycled through the layers. Notice the lack of connection between the via and the pour and Mid-Layer 2. I’m assuming this is because the vias are just connecting the ground pours?

[Marjeris Romero]

Hi,

Midtlayer 2 is the power plane of the board. VDD_SAM refers to the power domain for the Segger debugger chip used in the DK (ATSAM3U2CA).

And yes, it's recommended to use enough ground vias to connect the ground planes. This is specially important for RF designs, where having a big solid ground plane is very important. Our reference designs show what the distribution of the via holes may look like, or think about having one ground via every 3-5 mm.

If you are planing to do your own custom PCB using one of our nRF chips I recommend taking a look at the reference schematics and layout corresponding to the chip you are using. You can find these on the Nordic Infocenter, for example for the nRF52833 take a look at: https://infocenter.nordicsemi.com/index.jsp?topic=%2Fps_nrf52833%2Fref_circuitry.html

Pay close attention to the section "PCB guidelines" above.

Also you can take a look at this blogpost with general PCB design guidelines for the nRF52 series: https://devzone.nordicsemi.com/nordic/short-range-guides/b/hardware-and-layout/posts/general-pcb-design-guidelines-for-nrf52

Best regards,

Marjeris

[cheezballs]

Marjeris Romero said:

Midtlayer 2 is the power plane of the board. VDD_SAM refers to the power domain for the Segger debugger chip used in the DK (ATSAM3U2CA).

This makes sense, thank you!

Marjeris Romero said:

Our reference designs show what the distribution of the via holes may look like, or think about having one ground via every 3-5 mm.

Thanks for clarifying that! I am using one of the nRF52833 reference designs at the moment.

Marjeris Romero said:

Also you can take a look at this blogpost with general PCB design guidelines for the nRF52 series

This looks like a really useful resource.

Many thanks