BGA Escape pattern for nRF52840 0.35mm pitch WLCSP

[MSDEV]

I've been working with the nRF52840 WLCSP package for a month or two now, and in many ways it's a great compact chip. However, as my projects require more and more pins, I've run into a routing problem. Is there a recommended chip escape pattern that can route these pins out without using multiple layers of microvias? 

[Simonr]

Hi

I'm sorry, but we don't have any escape pattern for the WLCSP package using only two layers. We have the PCB layout example from the PS (available here), but other than that I'm afraid we don't have much.

Using traces thin enough to route between the pads should be fine, as long as your PCB fab support traces that thin. Also, be aware that you don't degrade the grounding of the IC during the design process. 

Best regards,

Simon

[MSDEV]

I don't need it on two layers, that would be very difficult! I have six layers to work with, I'm just trying to find a better escape pattern only using outer level (layers 1 and 6) microvias. Using more microvia levels increases the board cost massively due to the extra lamination steps. 

Routing between the pads would require fabrication resolution of 2mil or smaller which is also fairly difficult and expensive.