This is a 2 part question concerning the LFCLK input levels as well as how to test the LFCLK frequency against the HFCLK frequency to make sure they are consistent.
In this particular case, the nRF52840 is using the S140 BLE Soft Device and the LFCLK is connected to a SIT1532AC-J5-D14-32.768E – 32.768kHz XO (Standard) NanoDrive
Oscillator www.digikey.com/.../en. The J5 in the part number indicates it is a 75ppm clock. The D14 indicates it is 1.0V Hi 400mV low intended for direct coupled output. On my board it is connected directly to the P0.00 XL1 pin.
Oscillator www.digikey.com/.../en. The J5 in the part number indicates it is a 75ppm clock. The D14 indicates it is 1.0V Hi 400mV low intended for direct coupled output. On my board it is connected directly to the P0.00 XL1 pin.In case it matters, on my board, despite the spec, I measure the swing as being 0.3352V Lo to 0.6947V Hi.
I have set the low-swing xtal option using
NRF_CLOCK->LFCLKSRC = 131073; /* Select xtal source low swing */ followed by
NRF_CLOCK->TASKS_LFCLKSTART = 1; prior to calling nrf_sdh_enable_request().
NRF_CLOCK->TASKS_LFCLKSTART = 1; prior to calling nrf_sdh_enable_request().
The code then does a comparison between the NRF_RTC0->COUNTER, which I believe should track the LFCLK, to the 64MHz DWT->CYCCNT which is based on the board's 32MHz HF xtal.
At first I got what appeared to be relative counts consistent with the LFCLK in RC freerun (on 3 different boards values from 33.0KHz to 32.64KHz. I tried setting the values in sdk_config.h for NRFX_CLOCK_CONFIG_LF_SRC, CLOCK_CONFIG_LF_SRC, and NRF_SDH_CLOCK_LF_SRC to the various indicated possible values. I saw what I would expect to see as the perfect relation between HF and LF clocks when I select option 2 as expected, which instilled some confidence in the measurement of the relative clocks.
If sd_clock_hfclk_request(); is called after the vce_ble_softdevice_request_enable(), this allows getting an accurate measurement. I imagine the soft device is actively managing the HFCLK and making best effort corrections to the HF counter after it turns it off for periods, but I would appreciate a better understanding of why the LF frequency measurement relative to the HF based DWT->CYCCNT counter can be both higher and lower than the actual frequency.
My specific questions are:
1. What is the best hardware configuration: voltage swing option in combination with capacitive or direct coupling from the SIT1532 mems oscillator and is what I currently have valid for low-swing. Is it the optimal voltage swing option to get?
2. Does the soft device disable the HF automatically at any point if the sync clock is not selected. I ask this since my clock comparison code assumes the 64MHz clock is well behaved. If the 64MHz clock is being stopped, I would expect the measured LFCLK to be higher than it actually is, but this is not always what I see.
3. Is there a way to tell if the configuration is correct, but the LFCLK has not switched to the external clock and is still based on the RC oscillator because it has not detected the external clock? I want to do margin testing and need a clock loss criteria.
3. Is there a way to tell if the configuration is correct, but the LFCLK has not switched to the external clock and is still based on the RC oscillator because it has not detected the external clock? I want to do margin testing and need a clock loss criteria.
4. Is the DWT->CYCCNT expected to track the HFCLK when it is available and/or is it a more complicated combination of several clocks.
5. Final most important question is how you would recommend testing the external LFCLK input in a software only test. The test is needed to assess the health of the system throughout various reliability/environmental tests. Ideally the test could be run at any time without interfering with BLE communications, but a startup only test is possible if an "any time" test is not feasible.
Thanks,
Mitch
Thanks,
Mitch
