Hi,
I am using nRF52840 to communicate with the EEPROM. 24AA32AT-I/MC over I2C interface. The TWI scanner example detects the EEPROM address correctly for me .Now, I want to read/write the EEPROM.
As you know nrf and other drivers are deprecated in the SDK 16 and its recommended to use nrfx/latest drivers. I just wanted to know that out of the 4 TWI/I2C examples in SDK 16, which is best suited for my application for further development and does not use the legacy drivers.
Thanks
Karl,
I am using sdk 16, SES ,nRf52840 the simulated EEPROM example with an actual EEPROM (24AA32AT-I/MC) connected but I am not using any of the CLI/UART features of the example. Instead, I am trying to write direct TWI read and write functions, see attached code. In the write function, I am trying to write (0xff) to the EEPROM located at 0x52 address. During debugging and the the execution of write function, I am getting a DRV_TWI_ERR_ANACK error 0x0000820. I don't understand why I am getting this NACK . As you can see in the attached scope picture, the data pin is low on 9th clock pulse, hence it should be a perceived as ACK by the nRF52. One interesting fact is that by using the same hardware settings, I am able to poll EEPROM address (0x52) while using the twi scanner example.
If I remove all the breakpoints from the code and let it run its full course then I get the following condition, which I can only get out only by asserting the reset pin on nRF52.
NRF_BREAKPOINT_COND;
// On assert, the system can only recover with a reset.
/**
* Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
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* software without specific prior written permission.
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/**
* @file
* @brief File with example code presenting usage of drivers for TWIS slave and TWI in master mode
*
* @sa twi_master_with_twis_slave_example
*/
/**
* @defgroup twi_master_with_twis_slave_example Example code presenting usage of drivers for TWIS slave and TWI in master mode
*
* This code presents the usage of two drivers:
* - @ref nrf_twi_drv (in synchronous mode)
* - @ref nrf_twis_drv (in asynchronous mode)
*
* On the slave, EEPROM memory is simulated.
* The size of the simulated EEPROM is configurable in the config.h file.
* Default memory value of the device is 320 bytes. It is simulated using internal RAM.
* This RAM area is accessed only by simulated EEPROM so the rest of the application can access it
* only using TWI commands via hardware configured pins.
*
* The selected memory chip uses a 7-bit constant address. Word to access is selected during
* a write operation: first byte sent is used as the current address pointer.
*
* A maximum of an 8-byte page can be written in a single access.
* The whole memory can be read in a single access.
*
* When the slave (simulated EEPROM) is initialized, it copies the given part of flash
* (see EEPROM_SIM_FLASH_ADDRESS in config.h) into RAM (enabling the use of the slave for
* bootloader use cases).
*
* Many variables like length of sequential writes/reads, TWI instance to use, endianness of
* of slave bype addressing can be configured in config.h file
*
* Differences between real chip and simulated one:
* 1. Simulated chip has practically 0 ms write time.
* This example does not poll the memory for readiness.
* 2. During sequential read, when memory end is reached, there is no support for roll-over.
* It is recommended for master to assure that it does not try to read more than the page limits.
* If the master is not tracking this and trying to read after the page ends, then the slave will start to NACK
* for trying to over-read the memory. The master should end the transaction when slave starts NACKing, which could
* mean that the master has read the end of the page.
* 3. It is possible to write a maximum of EEPROM_SIM_SEQ_WRITE_MAX_BYTES bytes in a single
* sequential write. However, in simulated EEPROM the whole address pointer is incremented.
* In a real device, writing would roll-over in memory page.
*
* On the master side, we communicate with that memory and allow write and read.
* Simple commands via UART can be used to check the memory.
*
* Pins to short:
* - @ref TWI_SCL_M - @ref EEPROM_SIM_SCL_S
* - @ref TWI_SDA_M - @ref EEPROM_SIM_SDA_S
*
* Supported commands will be listed after Tab button press.
* @{
*/
#include <stdbool.h>
#include <stdint.h>
#include <stdio.h>
#include <ctype.h>
#include <string.h>
#include "config.h"
//#include "eeprom_simulator.h"
#include "nrf_drv_twi.h"
#include "nrf_gpio.h"
#include "app_error.h"
#include "nrf.h"
#include "bsp.h"
#include "app_util_platform.h"
#include "app_timer.h"
#include "nrf_drv_clock.h"
#include "nrf_delay.h"
#define EEPROM_ADD 0x52
//#include "nrf_log.h"
//#include "nrf_log_ctrl.h"
//#include "nrf_log_default_backends.h"
//#include "nrf_cli.h"
//#include "nrf_cli_uart.h"
//NRF_CLI_UART_DEF(m_cli_uart_transport, 0, 64, 16);
//NRF_CLI_DEF(m_cli_uart, "uart_cli:~$ ", &m_cli_uart_transport.transport, '\r', 4);
/**
* @brief TWI master instance.
*
* Instance of TWI master driver that will be used for communication with
* EEPROM memory.
*/
static const nrf_drv_twi_t m_twi_master = NRF_DRV_TWI_INSTANCE(MASTER_TWI_INST);
/**
* @brief Initialize the master TWI.
*
* Function used to initialize the master TWI interface that would communicate with simulated EEPROM.
*
* @return NRF_SUCCESS or the reason of failure.
*/
static ret_code_t twi_master_init(void)
{
ret_code_t ret;
const nrf_drv_twi_config_t config =
{
.scl = TWI_SCL_M,
.sda = TWI_SDA_M,
.frequency = NRF_DRV_TWI_FREQ_100K,
.interrupt_priority = APP_IRQ_PRIORITY_HIGH,
.clear_bus_init = false
};
ret = nrf_drv_twi_init(&m_twi_master, &config, NULL, NULL);
if (NRF_SUCCESS == ret)
{
nrf_drv_twi_enable(&m_twi_master);
}
return ret;
}
/**
* The beginning of the journey
*/
int main(void)
{
uint8_t clear_val = 0xFF;
uint8_t addr = 0x00;
ret_code_t err_code;
uint8_t tx_buffer[EEPROM_ADDRESS_LEN_BYTES + EEPROM_SEQ_WRITE_MAX_BYTES];
//Transmit buffer declaration
uint8_t rx_data;
//Transmit buffer declaration
APP_ERROR_CHECK(err_code);
/* Initializing TWI master interface for EEPROM */
err_code = twi_master_init();
APP_ERROR_CHECK(err_code);
/* Initializing clock */
err_code = nrf_drv_clock_init();
APP_ERROR_CHECK(err_code);
/* Initializing low freqiency clock */
nrf_drv_clock_lfclk_request(NULL);
/* Initializing Timer */
err_code = app_timer_init();
APP_ERROR_CHECK(err_code);
memcpy(tx_buffer, &clear_val, EEPROM_SEQ_WRITE_MAX_BYTES);
//Load the Tx buffer with 0xFF
err_code = nrf_drv_twi_tx(&m_twi_master, EEPROM_ADDR, tx_buffer, sizeof(tx_buffer), false);
//Write buffer data to EEPROM
APP_ERROR_CHECK(err_code);
err_code = nrf_drv_twi_rx(&m_twi_master, EEPROM_ADDR, &rx_data, 2);
//Read from EEPROM
APP_ERROR_CHECK(err_code);
/* Main loop */
while (1)
{
nrf_delay_ms(100);
__WFI();
}
}
