PAN #32. TIMER: One CC register is not able to generate an event for the second of two subsequent counter/ timer values.

[Dominik Hochwimmer]

Hi everone!

I need to get a timer setup which repeatly fires 2 IRQs. The first i.e. after a timer count cc0=500 and the 2nd count cc0=700. After 700 ticks the timer value (count) should become cleared and then cc0=500 -> 700 -> 500 ...

I could achieve this "timeframe" by using 2 ccs (cc0 = 500, cc1 = 700.... short cc1->clear timer0 activated) To save cc1 I tried to use cc0 for both values instead, unfortunatly i couldnt get it to work this way.

Now I am wondering if this got to do with PAN32 (nrf51822)or if i missed something in my code.

Could someone please clarify if PAN 32 means that the 2nd event using only 1 cc register is only NOT fired if ie. cc0 = 500 and next it becomes set to cc0=501 or if it would also my case (cc0 = 500 and then cc0 = 700).

Thanks in advance! RGDS Dominik

[Ole Morten]

Unfortunately, I don't have time to test it right now, but as far as I've understood, the PAN applies only if you have CC = 500 and then tries to use CC = 501.

Let me know if you see anything suggesting otherwise, so that I can look further into it over the weekend!

[Dominik Hochwimmer]

Thanks Ole,

for the moment thats all I needed to know! ;) For now I will go on using a second cc-register, in future i may give it another try and will come up with some example code.

RGDS