DAP acquire sequence and maximum CLK speed

[lo]

Hello,

I am designing a test jig with embedded gang programmer (10 targets) for our NRF52840 module and i have issue with reliable target acquisition, i would like to know what is the expected acquisition sequence (delay time for reset and timing / state of SW-CLK and SW-IO for acquisition) and the maximum allowed CLK speed.

Thank you.

[Susheel Nuguru]

I do not have these numbers with me, but I have asked my colleague regarding this who might have some estimates. I will be back to you when I have some response from him.

[Susheel Nuguru]

seems like the person who can answer this is on summer vacation, we need to wait until he comes back.

Sorry for the inconvenience 

[lo]

Hello,

IS there any update on this ticket? its been 3 month...

[Einar Thorsrud]

Hi,

I am sorry for the late reply. The maximum frequency for the CLK is 8 MHz (see electrical specification for the CTRL-AP). I have not found answers about the timing though, but I will attempt to get it and get back to you.

[lo]

thank you for this useful information

[Einar Thorsrud]

Regarding the acquisition sequence we do not have numbers specific for SWD. However, the t_R2ON numbers from the Device startup times table can be used. Please note that these numbers are not entirely accurate for SWD as parts of the logic is different, but it should be in the right ballpark.