WDT: store debug data for reboot

[lubedence]

Hi,

I have an unkown problem in my nrf52 application. It happens rarely, so I have no idea where to look at the moment. The only thing I know is that the WDT works and resets the device (looking at RESETREAS register). 

My idea would be to store some debug data (i.e. some sort of id so I know what the last checkpoint or called function is). 

First I tried to use the GPREGRET register to store this kind of data, but WDT reset will reset this register.

After that I tried to store the data to flash as soon as wdt_event_handler is called. This does not work either, I guess because the max amount of time I have in WDT interrupt is two cycles of 32768[Hz] clock.

So my question is: how can I persist debug data efficiently and read it after WDT reset?

[Edvin]

Hello,

Have you tried to log something in the WDT event handler? As you say, you only have two cycles of the LFCLK, but if you use RTT logging I believe you will be able to log some information. (UART is too slow, so no point in using that). 

From where do you feed the WDT? Is it possible that you only feed it in certain events, and that you simply didn't have any events firing causing the WDT to time out?

What is your watchdog configuration? (pause/run in sleep/halt) You can check this by reading out the CONFIG register after the WDT is initialized. 

Best regards,

Edvin

[lubedence]

Hi,

I am pretty sure it is not a WDT configuration problem. Even though, I would be still interested how to tackle such a problem.

Regarding UART: already tried that, is too slow :(

Regarding RTT: I would be very happy if I do not need to use RTT + JLink, but I guess I have to try that as a last resort. 

Isn't there another solution?

Thanks

[Edvin]

Hello,

A colleague of mine said that you can try this solution:

https://devzone.nordicsemi.com/f/nordic-q-a/30075/saving-the-location-of-watchdog-timeout

The RAM is not reset during a WDT reset. 

BR,

Edvin