Nordic Trace Buffer

[Christopher Mason]

The 51822 PS mentions a "Nordic Trace Buffer" but doesn't seem to elaborate. I assume this is similar to the Cortex Micro Trace Buffer? Is there any more documentation available? Thanks.

-c

[Chinook]

Very late answer. Have just played with NTB in revision 2 chip and found the following. Perhaps it will be useful for someone.

The Special Function Register layout is similar to that of Cortex-M0+ MTB (and probably is the same as for ARM Basic Branch Buffer). Exceptions are:

• EN bit is moved from MASTER[31] to POSITION[0],
• WRAP — POSITION[2] —> MASTER[31],
• HALTREQ — MASTER[9] —> POSITION[1],
• MASK field should have value 1 higher than for MTB,
• bits RAMPRIM, SFRWPRIV, TSTOPEN, TSTARTEN in MASTER register are removed (always read as zero),
• S bit in trace packet is always zero,
• there is one more bit with unknown meaning in FLOW[2] (reserved in MTB).

The base address of the NTB SFR region is 0xF0002000 (Can be obtained from the CoreSight ROM table). SRAMBASE is 0x20000000, AWIDTH is 14 (for 16kB RAM chip), so the whole RAM (any part of it) can be used to store trace packets.

Every branch, which target is in RAM, takes two additional clock cycles to store trace data (When branch target is in FLASH the trace data is stored in parallel with prefetch thus having zero overhead). Have not yet found other differences in behavior.

[samsonc]

Did you ever get to test further? Your post was super informative - I was able to enable the trace buffer, and dump traces to RAM using what you posted. I used Keil and a debug script to set up the trace buffer registers. While I could always view the memory using a Segger probe, I could only get Keil to automatically parse the trace buffer with a Keil uLink. Other features relying on trace abilities did not function in Keil for some reason. Anyone get trace to work on the nRF51 or nRF52 nicely on an IDE on any platform?

[Chinook]

Nope, I didn't try/use any support for tracing in an IDE. Though it's worth to pay attention to it.