Maximum number of interrupt enabled pins?

[Florin]

Hi,

Sorry for the noob questions but I'm trying to understand the GPIOTE abstraction and terminology, specifically the events, interrupts and tasks. My understanding is that GPIOTE can have events (signal transitions on input pins) generating interrupts that can be processed via GPIOTE_IRQHandler that can be sorted out by inspecting the RF_GPIOTE->EVENTS_IN registers . There are a total of four events that can be configured to trigger interrupts, using the NRF_GPIOTE->CONFIG[0..3] registers (channels?). I understand that the sense mechanism can also be used to detect pin changes but doesn't track the actual pin that transitioned state. Does this mean that I can configure only four input pins with interrupt capability?

Thanks! florin

PS: A GPIO task can set/clear another pin as a result of an event but it didn't seem relevant here. Anyway, can it only used in conjunction with PPI's Task end-point?

[Hung Bui]

Hi,

There are 2 type of event for GPIO pins: port event and pin events. You can find the definition at section 14.1.1 and 14.1.2

Basically for PIN events you can have maximum 4 pin events, each for one GPIO pin (so max 4 pins at a time) and you can detect which pin cause the event. PORT event, on the other hand, can be set for all GPIO pins at the same time, with the DETECT signal (sense mechanism).

You will get the PORT event when any pin issues the DETECT signal. You will not be be able to directly detect the pin, but can pass through all the pins that enabled SENSE and read the value of each pin to detect which causes the signal.

One main difference that worth mentioning is that PORT event and SENSE mechanism don't require 16MHz oscillator which mean you can have very low power consumption, when PIN event, when enabled, will consume about 1mA.

[Florin]

Thanks for the detailed answer!

On the PORT even I still have two questions:

1. If I configure two pins to sense a high level, how can I detect which pin raised the interrupt if one pin stays high the whole time while the other one transitions? (specifically, NRF_GPIO->IN will report both pins to 1, how can I tell them apart?)
2. What if both pins remain high, are interrupts still generated or are they generated on transitions only (as Fig.15 pg 55 of the Reference Manual suggests)?

There is another discussion here https://devzone.nordicsemi.com/index.php/nrf51422-sense-mechanism-detect-more-than-one-pin but it's still not clear to me...

Thanks again! florin