Power down/on a RAM section

[Seung]

Hi,

I'm trying to find a way to power down and on again a RAM section, but I haven't had any luck finding.

In the SDK examples, there's a RAM retention example only, but I'm interested in power down a RAM section.

If there's any documents or examples, it would be great.

Best Regards,

[Vidar Berg]

Hi,

I'm not aware of any SDK examples that powers down blocks in System ON, but here are a couple of threads that I think you will find helpful: https://devzone.nordicsemi.com/f/nordic-q-a/64907/nrf52840---understanding-ram-ahb-slaves-and-sections and https://devzone.nordicsemi.com/f/nordic-q-a/39396/nrf52840-ram-retention-in-system-on-mode/152628#152628. Please take a look at those, and let me know if anything is unclear.

And remember that both GCC and SES place the call stack at the end of RAM so be careful not to turn off retention on those. An idea may be to reduce the RAM length in your linker so and turn off the RAM blocks that come after.

Best regards,

Vidar

[Seung]

Hi Vidar,

Thanks for the answer. I have two more questions regarding the second link.

Based on my understanding, the following code changes values of registers for section 0 and 1 in RAM0, and the system is going to turn off the power of RAM (typically within 10 cycles?).

NRF_POWER->RAM[0].POWERCLR = 0x3; // 00000011 in binary

At this point, after changing the values, how can I check whether the sections are powered down or not? Can I simply assume that the power is down after 10 cycles?

Another question is how can I turn it on again? By putting zeros to POWERCLR or putting ones to POWERSET?

NRF_POWER->RAM[0].POWERCLR = 0; // 00000000 in binary

or

NRF_POWER->RAM[0].POWERSET = 0x3; // 00000011 in binary

Best Regards,

Seung

[Vidar Berg]

Hello Seung,

Yes, writing 0x3 to RAM[0].POWERCLR will turn off section 0 and 1 in RAM0. I'm not sure how many cycles it takes, but you can read back the RAM[0].POWER register to check the current setting. This should work as a synchronization barrier as well. Note that the RAM block will be powered when the chip is in debug interface mode.

You can write 0x3 to RAM[0].POWERSET to enable the RAM sections again as you said. NRF_POWER->RAM[0].POWERCLR = 0 will not have any effect.

Best regards,

Vidar

[Seung]

Hi Vidar,

I didn't know that RAM blocks are powered when the chip is in debug mode. That explains why I was unavailable to power down RAM sections. I will test on release mode.

Hope it can resolve my issue.

Thanks for your help.

Best Regards,

Seung