Hi all,
I'm having some trouble on figuring out how the UICR behaves and what I can expect from it. I am trying to lock the UICR from further modication. Based on the documentation I figured this should be possible by writing all registers twice.
Citing the NVMC documentation of the NRF52:
User information configuration registers (UICR) are written in the same way as flash. After UICR has been written, the new UICR configuration will only take effect after a reset. UICR can only be written nWRITE number of times before an erase must be performed using ERASEUICR or ERASEALL. The time it takes to write a word to UICR is specified by tWRITE. The CPU is halted if the CPU executes code from the flash while the NVMC is writing to the UICR.
And the documentation quantifies nWRITE in a table below:
nWRITE, Number of times a 32-bit word can be written before erase, 2
nENDURANCE, Erase cycles per page, 10000
tWRITE, Time to write one 32-bit word, 41 µs
tERASEPAGE, Time to erase one page, 85 ms
tERASEALL, Time to erase all flash, 169 ms
Based on this information I'd expect that if I write a since register twice, and subsequent write will be ignored or raises an error. However, this is not what I observed using the code-fragment below:
nrf_nvmc_write_word(
(uint32_t) &NRF_UICR->CUSTOMER[7],
0xFFFFFF00
);
nrf_nvmc_write_word(
(uint32_t) &NRF_UICR->CUSTOMER[7],
0xFFFF0000
);
nrf_nvmc_write_word(
(uint32_t) &NRF_UICR->CUSTOMER[7],
0x00FF0000
);
The register (being 0xFFFFFFFF initially) ends up having the value 0x00FF0000. Instead of 0xFFFF0000 which I'd expect. The UICR appears to behave like normal flash...
Is there a way to write-lock the UICR? Also, what does this "nWRITE, Number of times a 32-bit word can be written before erase, 2" really mean?
Kind Regards,
Jaap
