Softdevice hanging at startup

[Hugo Habicht]

Hi all,

I am having a problem with the startup of the software on an nRF52840. It works fine on an EVM but not on our own board. The software is hanging in the softdevice s140 before even reaching main() (on some boards only). I can see in the debugger when I stop the software that it is in address 0x2ff8 waiting for an external interrupt.  What is is waiting for? What are we missing?

And I have asked the question before without ever getting an answer: IS THERE ANY DOCUMENTATION OR SOURCE CODE OF THIS MAGIC BLACK BOX CALLED SOFTDEVICE AVAILABLE?

Any help would be appreciated.

Regards,

[Hugo Habicht]

Hi Jørgen,

changed to the RC oscillator but that did not make a difference. Could have guessed that before because the oscillator init is done in main().

In my case the softdevice is hanging BEFORE reaching main() (see first post).

So since your documentation contains nothing about what is happening inside the softdevice (only API) you have to help me on that one. Any ideas? What is it waiting for in address 0x2ff6?

I believe it has to be hardware related because the software (basically the BLE hrs example) is running fine on the Nordic EVM.

Regards,

p.s.: seems to be waiting for something to happen in bit 4 of a register on address 0xe000e204 which is not documented (another Nordic black box or I am too stupid to find it).

[Jørgen Holmefjord]

Which SDK and softdevice versions are you using? Is this a "clean project" from an SDK release, or something you have ported from a previous SDK version?

0xE000E204 is not a "Nordic Black Box", this is one of the ARM Cortex M4 NVIC_ISPR (Interrupt Set-Pending Registers) registers.

[Hugo Habicht]

Hi Jørgen,

I believe the SDK is version nRF5_SDK_17.0.0_9d13099 although I could not confirm that in any of the source files; there are no version numbers in them.

The example is the pca10056 board from the same SDK; we never installed an older version or ported anything.

Softdevice version is s140_nrf52_7.0.1.

Thanks for the hint with the NVIC register. But since this is ARM core documentation, where is the Nordic assignment for the nRF52840? Could not find anything in the data sheet. What is bit 4 in NVIC_ISPR1?

And why would the startup code (unfortunately located in the softdevice) wait for an interrupt?!? Or am I missing something?

Regards,

[Jørgen Holmefjord]

The IRQ numbers are defined in the MDK, in the file modules\nrfx\mdk\nrf52840.h:

typedef enum {
/* =======================================  ARM Cortex-M4 Specific Interrupt Numbers  ======================================== */
  Reset_IRQn                = -15,              /*!< -15  Reset Vector, invoked on Power up and warm reset                     */
  NonMaskableInt_IRQn       = -14,              /*!< -14  Non maskable Interrupt, cannot be stopped or preempted               */
  HardFault_IRQn            = -13,              /*!< -13  Hard Fault, all classes of Fault                                     */
  MemoryManagement_IRQn     = -12,              /*!< -12  Memory Management, MPU mismatch, including Access Violation
                                                     and No Match                                                              */
  BusFault_IRQn             = -11,              /*!< -11  Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory
                                                     related Fault                                                             */
  UsageFault_IRQn           = -10,              /*!< -10  Usage Fault, i.e. Undef Instruction, Illegal State Transition        */
  SVCall_IRQn               =  -5,              /*!< -5 System Service Call via SVC instruction                                */
  DebugMonitor_IRQn         =  -4,              /*!< -4 Debug Monitor                                                          */
  PendSV_IRQn               =  -2,              /*!< -2 Pendable request for system service                                    */
  SysTick_IRQn              =  -1,              /*!< -1 System Tick Timer                                                      */
/* ==========================================  nrf52840 Specific Interrupt Numbers  ========================================== */
  POWER_CLOCK_IRQn          =   0,              /*!< 0  POWER_CLOCK                                                            */
  RADIO_IRQn                =   1,              /*!< 1  RADIO                                                                  */
  UARTE0_UART0_IRQn         =   2,              /*!< 2  UARTE0_UART0                                                           */
  SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn=   3,  /*!< 3  SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0                                      */
  SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn=   4,  /*!< 4  SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1                                      */
  NFCT_IRQn                 =   5,              /*!< 5  NFCT                                                                   */
  GPIOTE_IRQn               =   6,              /*!< 6  GPIOTE                                                                 */
  SAADC_IRQn                =   7,              /*!< 7  SAADC                                                                  */
  TIMER0_IRQn               =   8,              /*!< 8  TIMER0                                                                 */
  TIMER1_IRQn               =   9,              /*!< 9  TIMER1                                                                 */
  TIMER2_IRQn               =  10,              /*!< 10 TIMER2                                                                 */
  RTC0_IRQn                 =  11,              /*!< 11 RTC0                                                                   */
  TEMP_IRQn                 =  12,              /*!< 12 TEMP                                                                   */
  RNG_IRQn                  =  13,              /*!< 13 RNG                                                                    */
  ECB_IRQn                  =  14,              /*!< 14 ECB                                                                    */
  CCM_AAR_IRQn              =  15,              /*!< 15 CCM_AAR                                                                */
  WDT_IRQn                  =  16,              /*!< 16 WDT                                                                    */
  RTC1_IRQn                 =  17,              /*!< 17 RTC1                                                                   */
  QDEC_IRQn                 =  18,              /*!< 18 QDEC                                                                   */
  COMP_LPCOMP_IRQn          =  19,              /*!< 19 COMP_LPCOMP                                                            */
  SWI0_EGU0_IRQn            =  20,              /*!< 20 SWI0_EGU0                                                              */
  SWI1_EGU1_IRQn            =  21,              /*!< 21 SWI1_EGU1                                                              */
  SWI2_EGU2_IRQn            =  22,              /*!< 22 SWI2_EGU2                                                              */
  SWI3_EGU3_IRQn            =  23,              /*!< 23 SWI3_EGU3                                                              */
  SWI4_EGU4_IRQn            =  24,              /*!< 24 SWI4_EGU4                                                              */
  SWI5_EGU5_IRQn            =  25,              /*!< 25 SWI5_EGU5                                                              */
  TIMER3_IRQn               =  26,              /*!< 26 TIMER3                                                                 */
  TIMER4_IRQn               =  27,              /*!< 27 TIMER4                                                                 */
  PWM0_IRQn                 =  28,              /*!< 28 PWM0                                                                   */
  PDM_IRQn                  =  29,              /*!< 29 PDM                                                                    */
  MWU_IRQn                  =  32,              /*!< 32 MWU                                                                    */
  PWM1_IRQn                 =  33,              /*!< 33 PWM1                                                                   */
  PWM2_IRQn                 =  34,              /*!< 34 PWM2                                                                   */
  SPIM2_SPIS2_SPI2_IRQn     =  35,              /*!< 35 SPIM2_SPIS2_SPI2                                                       */
  RTC2_IRQn                 =  36,              /*!< 36 RTC2                                                                   */
  I2S_IRQn                  =  37,              /*!< 37 I2S                                                                    */
  FPU_IRQn                  =  38,              /*!< 38 FPU                                                                    */
  USBD_IRQn                 =  39,              /*!< 39 USBD                                                                   */
  UARTE1_IRQn               =  40,              /*!< 40 UARTE1                                                                 */
  QSPI_IRQn                 =  41,              /*!< 41 QSPI                                                                   */
  CRYPTOCELL_IRQn           =  42,              /*!< 42 CRYPTOCELL                                                             */
  PWM3_IRQn                 =  45,              /*!< 45 PWM3                                                                   */
  SPIM3_IRQn                =  47               /*!< 47 SPIM3                                                                  */
} IRQn_Type;

Bit 4 of NVIC_ISPR1 would correspond to SPIM2_SPIS2_SPI2_IRQn or RTC2_IRQn, depending on if you started counting from 0 or from 1. None of these should be related to the softdevice.

As far as I know, the softdevice should not run startup code, it only handles forwarding of interrupts from MBR to application (see Exception model). The SystemInit code is found in the MDK as well (modules\nrfx\mdk\system_nrf52840.c).

[Hugo Habicht]

Hi Jørgen,

last time I checked Arm architecture specifies LSB as bit 0, so in this case your softdevice is waiting for an RTC2 interrupt. Why is that?

Also, does the hrs example include a boot loader? If yes, where can I find information about same? The MBR/ Bootloader documentation is sparse; I could only find addresses but no structure contents or description or what happens at startup. Or do I have to search all that in the source myself?

Regards,