Running an application that is using a 32 Mhz SPIM3 interface and it is working fine on our custom board.
As part of the interface testing, a logic analyzer was used to make sure all the chip interface specifications are met.
All the SPIM output pins are configured with a H0H1 drive strength.
Was wondering if there is anyway to get rid of the 5-7 ns glitches between the bytes as seen on the logic analyzer trace.
Key SPIM3 config details provided below and the SPIM3 priority is set to 3.
static void spim_init(void)
{
uint32_t
err;
spi_config.frequency = NRF_SPIM_FREQ_32M; //NRF_SPIM_FREQ_250K;
spi_config.ss_pin = CC_NCS_PIN;
spi_config.miso_pin = CC_MISO_PIN;
spi_config.mosi_pin = CC_MOSI_PIN;
spi_config.sck_pin = CC_SCK_PIN;
spi_config.use_hw_ss = true;
spi_config.ss_active_high = false;
APP_ERROR_CHECK(nrfx_spim_init(&spi, &spi_config, spim_event_handler, NULL));
spi_xfer_done = true;
NRF_LOG_INFO("\nNRFX SPIM started.");
NRF_P0->PIN_CNF[CC_SCK_PIN] &= ~GPIO_PIN_CNF_DRIVE_Msk; // Clear the drive config
NRF_P0->PIN_CNF[CC_SCK_PIN] |= (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos); // Set the new drive con
NRF_P0->PIN_CNF[CC_MOSI_PIN] &= ~GPIO_PIN_CNF_DRIVE_Msk; // Clear the drive config
NRF_P0->PIN_CNF[CC_MOSI_PIN] |= (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos); // Set the new drive con
NRF_P0->PIN_CNF[CC_NCS_PIN] &= ~GPIO_PIN_CNF_DRIVE_Msk; // Clear the drive config
NRF_P0->PIN_CNF[CC_NCS_PIN] |= (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos); // Set the new drive con
}
