not occur 'NRF_EVT_POWER_FAILURE_WARNING'

[Sawada]

soft device:s132
sdk:15.3.0
board:nRF52832 board (taiyo yuden EYSHCNZWZ)

Unable to receive event 'NRF_EVT_POWER_FAILURE_WARNING'
I implemented the following, but the event does not occur even if the voltage is V2.8 or less.
The value of POFCON after calling sd_power_pof_threshold_set (NRF_POWER_THRESHOLD_V28) is 0x1F.

Do you know the reason?

Implementation code

NRF_SDH_SOC_OBSERVER(m_soc_observer, 0, pof_evt_dispatch, NULL);

void pof_evt_dispatch(uint32_t sys_evt, void * p_context)
{
if (sys_evt == NRF_EVT_POWER_FAILURE_WARNING)
{
sd_nvic_SystemReset();
}
}

static void power_pof_init(void)
{
ret_code_t err_code = sd_power_dcdc_mode_set(NRF_POWER_DCDC_ENABLE);
APP_ERROR_CHECK(err_code);
err_code = sd_power_pof_enable(1);
APP_ERROR_CHECK(err_code);
err_code = sd_power_pof_threshold_set(NRF_POWER_THRESHOLD_V28);
APP_ERROR_CHECK(err_code);

}

sdk_config.c

sdk_config.c

// <e> NRF_SDH_SOC_ENABLED - nrf_sdh_soc - SoftDevice SoC event handler
//==========================================================
#ifndef NRF_SDH_SOC_ENABLED
#define NRF_SDH_SOC_ENABLED 1
#endif
// <h> SoC Observers - Observers and priority levels

//==========================================================
// <o> NRF_SDH_SOC_OBSERVER_PRIO_LEVELS - Total number of priority levels for SoC observers.
// <i> This setting configures the number of priority levels available for the SoC event handlers.
// <i> The priority level of a handler determines the order in which it receives events, with respect to other handlers.

#ifndef NRF_SDH_SOC_OBSERVER_PRIO_LEVELS
#define NRF_SDH_SOC_OBSERVER_PRIO_LEVELS 2
#endif

// <h> SoC Observers priorities - Invididual priorities

//==========================================================
// <o> BLE_ADV_SOC_OBSERVER_PRIO
// <i> Priority with which SoC events are dispatched to the Advertising module.

#ifndef BLE_ADV_SOC_OBSERVER_PRIO
#define BLE_ADV_SOC_OBSERVER_PRIO 1
#endif

// <o> BLE_DFU_SOC_OBSERVER_PRIO
// <i> Priority with which BLE events are dispatched to the DFU Service.

#ifndef BLE_DFU_SOC_OBSERVER_PRIO
#define BLE_DFU_SOC_OBSERVER_PRIO 1
#endif

// <o> CLOCK_CONFIG_SOC_OBSERVER_PRIO
// <i> Priority with which SoC events are dispatched to the Clock driver.

#ifndef CLOCK_CONFIG_SOC_OBSERVER_PRIO
#define CLOCK_CONFIG_SOC_OBSERVER_PRIO 0
#endif

// <o> POWER_CONFIG_SOC_OBSERVER_PRIO
// <i> Priority with which SoC events are dispatched to the Power driver.

#ifndef POWER_CONFIG_SOC_OBSERVER_PRIO
#define POWER_CONFIG_SOC_OBSERVER_PRIO 0
#endif

[Einar Thorsrud]

Hi,

I do not immediately understand why you do not get a NRF_EVT_POWER_FAILURE_WARNING. How have you verified that it is the case? I noticed that you call sd_power_pof_enable() before sd_power_pof_threshold_set() which is a bit odd, but should not be a problem. Do you enable the SDH which you use here, or could it be a problem there? Can you share more code (ideally a working project for a DK) so that I can see what you have done and potentially attempt to reproduce the issue on my side?

[Sawada]

I changed the process.
But the behavior did not change

static void power_pof_init(void)
{
    ret_code_t err_code;
	uint32_t p_is_running;
	err_code = sd_clock_hfclk_request();
    APP_ERROR_CHECK(err_code);
	do { 
		sd_clock_hfclk_is_running(&p_is_running); 
	}while(p_is_running==0);
	
    err_code = sd_power_dcdc_mode_set(NRF_POWER_DCDC_ENABLE);
    APP_ERROR_CHECK(err_code);
    err_code = sd_power_pof_threshold_set(NRF_POWER_THRESHOLD_V28);
    APP_ERROR_CHECK(err_code);
    err_code = sd_power_pof_enable(1);
    APP_ERROR_CHECK(err_code);
}

SDH is already enabled before running power_pof_init().

/**@brief Function for initializing the BLE stack.
 *
 * @details Initializes the SoftDevice and the BLE event interrupts.
 */
void ble_stack_init(void)
{
    ret_code_t err_code;

    err_code = nrf_sdh_enable_request();
    sys_AppErrorCheck(err_code);

     // Configure the BLE stack by using the default settings.
    // Fetch the start address of the application RAM.
    uint32_t ram_start = 0;
    err_code = nrf_sdh_ble_default_cfg_set(APP_BLE_CONN_CFG_TAG, &ram_start);
    sys_AppErrorCheck(err_code);

    // Enable BLE stack.
    err_code = nrf_sdh_ble_enable(&ram_start);
    sys_AppErrorCheck(err_code);

    // Register a handler for BLE events.
    NRF_SDH_BLE_OBSERVER(m_ble_observer, APP_BLE_OBSERVER_PRIO, ble_evt_handler, NULL);
}

Confirmed that the following SOC events could be received
That's why SOC observers are also working
・ NRF_EVT_HFCLKSTARTED
・ NRF_EVT_FLASH_OPERATION_SUCCESS

You may be worried about the description of the URL below.
Do I have to enable other features such as HLCFK settings and CLOCK?
infocenter.nordicsemi.com/index.jsp

Power-fail comparator
To save power, the power-fail comparator is not active in System OFF or in System ON when HFCLK is not running.

[Sawada]

It is made so that the CPU does not sleep.
Therefore, it seems that no problem will occur.

The code below doesn't exist, is that the problem?

power_manage ();

[Sawada]

Sorry, power_manage() is local function.
This was just a function running sd_app_evt_wait () inside.

[Einar Thorsrud]

I see. In that case the CPU is not active and neither is the HFCLK unless there is another reason for it to be. So in this case you will not get POF events until the clock is enabled again for some reason (and the voltage is still below the configured level).

[Sawada]

	err_code = sd_clock_hfclk_request();
    APP_ERROR_CHECK(err_code);
	do { 
		sd_clock_hfclk_is_running(&p_is_running); 
	}while(p_is_running==0);

This code causes the following events to occur, so HFCLK appears to be enabled.

NRF_EVT_HFCLKSTARTED

Is there any sample code to enable CLOCK?

[Sawada]

It was found that NRF_EVT_POWER_FAILURE_WARNING occurred when the supply voltage of the DC Power supply was lowered to about 0.7V.
I don't know why it doesn't occur at 2.8V.

[Einar Thorsrud]

This does not make sense to me. 0.7 V is far below the operating conditions on the nRF. Are you confident about your HW configuration? Can you share the schematics of your board (including everything around the EYSHCNZWZ module, particuarlily anythign power related) and your test setup?