Can not connect to J-Flasher by Unexpexted core ID

[Andy kang]

When I tried to set up my J-Link Flash connection it gave me the message "Unexpected core ID.

First Dev Board R0.5  was normal. and marking of  nRF52840  chip was  QIAAD0 , 2004FC.

but Second Dev Board R0.6 is unnormal. and marking of  nRF52840  chip is QIAAD0 1934BQ

I have searched around and could not really find any information on this. Below is the output from J-Link Flash and error pop-up, Test config.Looking to see if I am doing something wrong or if I somehow need to change the expected Core ID the J-Link Flash expects.

===================================================================================================================

Application log started
- J-Flash V6.80a (J-Flash compiled May 29 2020 16:27:25)
- JLinkARM.dll V6.80a (DLL compiled May 29 2020 16:27:00)
Reading flash device list [C:\Program Files (x86)\SEGGER\JLink\ETC/JFlash/Flash.csv] ...
- List of flash devices read successfully (451 Devices)
Reading MCU device list ...
- List of MCU devices read successfully (7772 Devices)
Opening project file [C:/Program Files (x86)/SEGGER/JLink/Samples/JFlash/ProjectFiles/52840.jflash] ...
- Project opened successfully
Failed to open data file [C:\Program Files (x86)\SEGGER\JLink\Samples\JFlash\ProjectFiles\]...
Connecting ...
- Connecting via USB to probe/ programmer device 0
- Probe/ Programmer firmware: J-Link ARM / Flasher ARM V4 compiled Aug 21 2020 15:29:50
- Device "NRF52840_XXAA" selected.
- Target interface speed: 4000 kHz (Fixed)
- VTarget = 3.606V
- InitTarget() start
- InitTarget() end
- Found SW-DP with ID 0x2BA01477
- SWD speed too high. Reduced from 4000 kHz to 853 kHz for stability
- DPIDR: 0x29A01475
- Scanning AP map to find all available APs
- AP[2]: Stopped AP scan as end of AP map has been reached
- AP[0]: AHB-AP (IDR: 0x24750011)
- AP[1]: JTAG-AP (IDR: 0x00880000)
- Iterating through AP map to find AHB-AP to use
- AP[0]: Core found
- AP[0]: AHB-AP ROM base: 0xE00DF000
- CPUID register: 0x410DC041. Implementer code: 0x41 (ARM)
- Unknown core, assuming Cortex-M0
- Found Cortex-M0 r0p1, Little endian.
- Identified core does not match configuration. (Found: Cortex-M0, Configured: Cortex-M4)
- FPUnit: 6 code (BP) slots and 0 literal slots
- CoreSight components:
- ROMTbl[0] @ E00DF000
- Executing init sequence ...
- Initialized successfully
- Target interface speed: 4000 kHz (Fixed)
- WARNING: Unexpected core ID. (Found: 0x29A01475, Expected: 0x4BA00477, Mask: 0x0F000FFF)
- Found 1 JTAG device. Core ID: 0x29A01475 (None)

[James_Lee_K]

if i check your log, some log message shows that used chip core is different.

/*

- Unknown core, assuming Cortex-M0
- Found Cortex-M0 r0p1, Little endian.
- Identified core does not match configuration. (Found: Cortex-M0, Configured: Cortex-M4)

*/

You set up j-flash to write nRF52840 core.(cortex-m4).

But identified core is Cortex-m0.

is it correct that you connect correct nrf52840?

[Andy kang]

The connection is correct. 

All R0.6 boards are the same issue. (total 20ea)

The difference between Dev Board R0.5 and Dev. board R0.6 is only nRF52840 markng. 

I will change  to 2004FC from 1934BQ in the  Dev. board R0.6  and share the result.

If you have history of problems with unexected core ID. please share the information. 

thanks

[Kenneth]

These two chips should be identical (same build code, only different production date code). I suggest to check for soldering issue or other components may be out of spec/changed. You may try to pull the nRESET pin to VDD in case you have by accident enabled pin reset in firmware but don't have pin reset in the design. Swapping chips between good and bad boards (both ways) seems like a good suggestions.

Maybe try a lower interface speed, since I can see it says:
- SWD speed too high. Reduced from 4000 kHz to 853 kHz for stability

Do you see the same problem if using a standard j-link programmer with nrfjprog command line tool?