QSPI erase/write handling

[MKJ]

The documentation is unclear about QSPI handling:

If I issue a QSPI erase command then I receive confirmation that the erase command has been written to the external QSPI chip; the external QSPI chip will commence the erase operation.

Questions:

1) If I immediately issue a QSPI Write command then does the chip wait until the external QSPI chip has finished the erase?

2) If it does wait then  is there a timeout on this or will it hang forever?

[I believe that the chip issues read status instructions to determine the state of the external QSPI chip's WIP bit. However the documentation is unclear on how oftern it does this, if there is a timeout, etc]

[MKJ]

A related question is when is the status register of the external memory read into the top byte of the QSPI STATUS register? Is it updated periodically or only after read/write/erase?

[MKJ]

Also is the datasheet correct for the STATUS register - I see bit 1 set to '1'

[ovrebekk]

Hi Martin

1) If I immediately issue a QSPI Write command then does the chip wait until the external QSPI chip has finished the erase?

At the start of every command the QSPI interface will automatically read the status register, to make sure it doesn't read or write unless the device is idle. 

2) If it does wait then  is there a timeout on this or will it hang forever?

The QSPI should retry forever, yes. There is no defined timeout. 

Best regards
Torbjørn

[ovrebekk]

Hi 

MKJ said:

A related question is when is the status register of the external memory read into the top byte of the QSPI STATUS register? Is it updated periodically or only after read/write/erase?

As mentioned earlier this is read automatically before starting a write/read/erase operation, to ensure that the flash device is ready to accept new commands. 

MKJ said:

Also is the datasheet correct for the STATUS register - I see bit 1 set to '1'

You mean you see bit 1 set to 1 in the debugger?

Best regards
Torbjørn

[MKJ]

Torbjorn,

Thanks. When I read the QSPI STATUS register with the debugger I get, in hex, the following:

40029604 0A 00 00 42

The bottom byte has bit 3 set (QSPI Ready) but also has bit 1 set.

The upper byte (42) reflects the memory chip's status register which I validated independently as correct.

We get the same result if we read the STATUS register without the debugger.

Martin