Reset after sd_power_system_off in Non Debug mode

[exsurgo_ankit]

Hello,

We have a custom board designed using the ublox Anna B112 module which uses NRF52832. We are using it in open CPU mode and running our custom firmware. 

The VDD is 1.8V in our case. Whenever I have tried to enter deep sleep mode via 

sd_power_system_off() OR

nrf_power_system_off() OR

nrf_pwr_mgmt_shutdown(NRF_PWR_MGMT_SHUTDOWN_GOTO_SYSOFF) OR

NRF_POWER->TASKS_LOWPWR = 1; NRF_POWER->SYSTEMOFF = POWER_SYSTEMOFF_SYSTEMOFF_Enter;

The system resets right after. The RESETREAS register reads zero, suggesting that a power on or a brownout reset. I understand that 1.7V is minimum operational voltage.  My questions are:

1. How long does the VDD need to drop below that to trigger the reset?

2. How do I troubleshoot this issue? I have probed the VDD line using an oscilloscope have noticed a drop close to 1.7V for about 20 uSec.

I have reviewed all the threads on the forum on this issue. Ensured that the test is not in Debug mode, power cycled the unit, added an infinite loop after the call. 

Regards

[exsurgo_ankit]

We are trying to investigate the cause of the voltage drop. 

I have a capture of the voltage glitch and it is very small, also the spike isn't that big.

We will try increasing the voltage and report back.

[run_ar]

It looks as if the spike drops below the 1.7v minimum operating limit? The Power on reset circuit can be sensitive in this operating area. Did increasing the voltage help mitigate the issue?