Power off state of nRF51822 GPIOs

[Christopher Mason]

The nRF51 reference manual says that GPIO PIN_CNF registers are retained registers and that "a retained register is a register that will retain its value in system OFF mode, and through a reset depending on reset source."

I perhaps mistakenly took this to mean that if I set up a pin with a certain configuration, it would retain that configuration while power was removed from the chip. For instance, that if I set up a pin to have a pull up, that it would continue to be connected to the input power pin when all power was removed. Obviously, with no power connected to the chip, no voltage would be applied to the pin from the nRF side; but, it still be electrically connected (via resistor) to the positive supply line. Similarly for pull down (connected via a resistor to gnd), or for input disconnect (not connected to either -- floating).

I have an nRF51 GPIO pin that's connected to both an external device and a normally open push button, which is then connected to ground. This is intended to act as a momentary power switch. The external device provides a "weak internal pull-up forc[ing] a high state if [this pin] is left floating." This external device controls the power to the nRF chip. When the nRF51822 has power, and I set a pin as a pull up or pull down, or disconnect it, I observe the correct behavior. For instance, if I configure the pin as an input, I can read the state of the push button and I observe either 3.3V or 0 volts depending on the state of the push button. However, when the nRF51822 has all power removed, I read about 400mV on this pin when the button is open and 0V when closed.

I'm guessing that my understanding of "retained" is incorrect and that the power removed state of the GPIO pins is as a weak pulldown. I guess retained means that once power is reapplied to the chip and it resets, the pin goes back to having its pre-power off state (pull up, down, disconnect, etc). This makes sense now that I think about it since I guess the chip would need some power to retain the state of the transistors in the GPIO circuit.

Is this correct?

I've read this post, which helps, but, I'm still a little dense on what the IO circuit inside the nRF51 chip looks like, so I'm having trouble reasoning about it.

Thanks for helping my meager electronics understanding. :)

-c

[Ole Morten]

That the GPIO configuration registers are retained means that the configuration is kept through reset, as shown in the table in section 11.1.7.8 in the nRF51 Reference Manual. It does not mean that the configuration is kept when the device does not have power, since at that point, all data not written to flash is lost. Only the registers in FICR and UICR are flash registers, not the GPIO ones.

Therefore, if you completely remove power from the nRF51, all pins should be considered floating, and you should be careful not to apply any voltage to them. Doing so would be outside the "Absolute maximum ratings" for the chip, which states that any voltage above VDD + 0.3 V is too much, and in this case, VDD is 0. (In practice you are not likely to destroy the chip, but still.) Pulling a GPIO high when the power is off may actually result in the chip trying to run, which is most often undesirable.

If the sub-1 µA current the chip draws in system off isn't extremely important to you, it will therefore in most cases be much easier to just put the chip in system off instead of removing power. In system off, all GPIOs will keep their defined state.

[Bastiaan]

This makes sense. I'm implementing a totally-off-mode for shipping and storage. Thanks for the detailed response!

[Guest]

This makes sense. I'm implementing a totally-off-mode for shipping and storage. Thanks for the detailed response!

[Ole Morten]

No problem, but I'd be happy if you could sign in and accept the answer if you found it useful! :-)

[Sourabh Barve]

Is this same in case of nrf52?