52840 QIAA DC/DC ref layout and cap selection

[Namklak]

Hi,

I'm a firmware eng with an ancient history of h/w design.

We are in production with the nrf52840 but still do new designs.

This question is in reference to the 52840 QIAA DC/DC convertor (just running REG1) with a ble radio, power supply is generally battery.

I downloaded nRF52840-QIAA Reference Layout 1_1, and in Var4 they show 2 caps on DEC4 - a 1uF and 47nF.  This layout is already somewhat dated as the 1uF is 0603 and the 47nF is 0402 - and we are using all 0201.

Question: with modern ceramic 0201 caps that have very low ESR/ESL, why do I need 2 caps? 

Possible answer 1) This looks old school - years ago a 1uF cap was a tantalum or electrolytic, and had high ESR/ESL, so it had to be paired with a lower value ceramic. 

Possible answer 2) At the time of the ref layout, they couldn't get a 0201 1uF ceramic cap with low ESR/ESL, so they got a lower value cap that had a smaller form factor, that would enable them to put that cap physically right next to DEC4.

Or???

So really, if I can get a 1uF low ESR/ESL 0201 cap laid out right next to DEC4, so I really need to burden my layout and BOM with another cap?

Thanks,

Namklak

[ketiljo]

The reason for the smaller cap in parallel with the large cap is that the HF properties of the large cap isn't good enough to filter the harmonics of the DCDC converter good enough. The receiver sensitivity will be affected at some channels without this. 

It's true that modern ceramic caps have a lower ESR, but it's still not enough. If you want to omit the small cap, you can always do so, but you should measure sensitivity on all channels to be sure it's not affected. 

[Namklak]

Good info.  And close check of the spec sheet reveals the 47nF we are using does turn into an inductor at 50MHz as oppose to 12MHz of the 1uF - and also dips to a lower impedance of 10mOhms, compared to 30mOhns of the 1uF.

Something I didn't mention is when running the LDO with potentially a combo of bad layout and wrong caps, the LDO broke into oscillation at 12MHz.  So with our new board, with LDO on, we saw a 12MHz sideband on the 2.4G, and with DC/DC we saw an 8MHz sideband.  I think the DC/DC caused 8MHz sideband is explained by the switching freq of the DC/DC.

Do you have any comments on loading of the LDO to keep it stable?

On our board (we are going to change the layout) just using 1uF everywhere "fixed" the problem, but we'd like to know the LDO stability answer while we redesign our board.

Thanks.

[ketiljo]

You may see excessive spurious around the carrier if the 1 µF cap is placed near the DEC6 pin (E24). It must be close to the DEC4 pin (B5). Use the values in the reference schematic and make sure the placement in the schematic is correct for the layout as well.