SAADC + TIMER for repeated scan of two channels

[snoopy20]

Hi,

I'm setting up a timer to invoke (via PPI) the ADC in scan mode. It'll read to channels with MAXCNT of 10,000.

The ADC built in timer has a value from 

[80..2047]

Representing the frequency range (max being 200KHz). I imagine 200KHz represents the minimum sample hold time (3us) and 2us for additional set-up per channel. 

Questions

1.  for two channels should I be setting the timer for 100KHz, or will the second TASK_SAMPLE channel simply be ignored in SCAN mode?

2. if the hold time isn't 3us the timer frequency should ideally adjusted as to synchronise the TASK_SAMPLE to just after the last EVENT_STOP has occurred?

The datasheet shows an effective 9 bits of resolution at 200KHz with 3us sample which isn't good enough for my application. Where I'm potentially confused is by reducing the timer frequency wouldn't it just leave more space between the EVENT_STOP and the next TASK_SAMPLE trigger, that is, it would have no bearing on the actual ADC process. Therefore -

3. The maximum resolution of a 3us sample is 9 bit.

Thanks, Andrew

[Einar Thorsrud]

Hi Andrew,

1.  for two channels should I be setting the timer for 100KHz, or will the second TASK_SAMPLE channel simply be ignored in SCAN mode?

In scan mode (when more than 1 channels are enabled) you trigger the SAMPLE task once to sample all channels (see Scan mode in SAADC chapter in PS for details). So you would use 200 kHz here.

2. if the hold time isn't 3us the timer frequency should ideally adjusted as to synchronise the TASK_SAMPLE to just after the last EVENT_STOP has occurred?

Can you elaborate?

The datasheet shows an effective 9 bits of resolution at 200KHz with 3us sample which isn't good enough for my application. Where I'm potentially confused is by reducing the timer frequency wouldn't it just leave more space between the EVENT_STOP and the next TASK_SAMPLE trigger, that is, it would have no bearing on the actual ADC process. Therefore -

3. The maximum resolution of a 3us sample is 9 bit.

I assume you are referring to E_NOB from the SAADC electrical specifications: "Effective number of bits, differential mode, 12-bit resolution, 1/1 gain, 3 µs acquisition time, crystal HFCLK, 200 ksps". You should not read this is as a indication that either one of these parameters are particularly important (though some obviously more than others). Rather, this is the configuration used during characterization to find the effective number of bits.

If 9 bits is not enough, then you could perhaps consider a different approach, using burst mode (a form of oversampling). See this old post.

Einar

[snoopy20]

Hi,

If it's saying that at 3us only 9-bit is possible I can move down to 5us. 10 bit is the target now.

[Einar Thorsrud]

I see. That is not what it is saying. We have not characterized effective number of bits with different acquisition times. There is just this one configuration that has been characterised for effective number of bits. In any case the required acquisition time depends on source impedance. The higher source impedance, the longer acquisition time is needed.