FDS and write/erase flash cycles

[A.P]

Hi!

I've read a bit about the limitation of write/read cycles with the nRF52840. I the ~10,000 write/read cycles limit means after this many erases, the flash is no longer guaranteed to 'work properly'.

I have a few questions regarding this:

1. What does 'work properly' mean? will there be a problem with write operations, read operations or both? What kind of problems can be expected? (will I write 0xAB and sometimes the flash will contain 0xAC, or will the flash most likely contain 0xAB, but my read operation will return 0xAC?)

2. If the problem is with the flash read, rather than the flash write, does the FDS not 'deal' with this in any way? Meaning that if the CRC of the read data mismatches with the CRC of the flash data, will the FDS not -re-read the flash to get the 'correct value'?

3. Is there any way of knowing that my flash has started to deterioration? is there a count of 'erase' cycles kept somewhere which I can read to get an idea of how far I am from 10,000 writes?

4. Does the FDS guarantee a 'reasonably' equal distribution of write/erase cycles throughout the flash? meaning that if one flash segment has reached the 10,000 limit, the other flash segments are very close to the limit as well?

Thank you!

[A.P]

Hi all!
The interesting results are as follows:

We've run a flash write-read-erase test and limited the pages used so that the same page is written to, read from, and then erased. Each cycle wrote to the entire page with the following pattern:

A. Write 101010... read and compare. Erase.

B. Write 010101... read and compare. Erase.

C. Goto A.

We did this on 3 nRF52840s and found the following:

First chip failed after 790,397 cycles.

Second chip failed after 918,918 cycles.

Third chip failed after 1,102,080 cycles.

All subsequent reads returned an incorrect value from the flash.

So, it seems we can expect around 900 thousand cycles on each page flash, if my 3 samples are in any way a valid sample pool.
Does Nordic have the distribution graph for flash fails per write-erase cycles anywhere?

Is this expected to change in other chips? ex: nRF52833, nRF52820?

[Vidar Berg]

Thanks for the update. Intereseting results!

A.P said:

First chip failed after 790,397 cycles.

Second chip failed after 918,918 cycles.

Third chip failed after 1,102,080 cycles.

  Does this correspond to the number of erase cycles on one flash page?

A.P said:

So, it seems we can expect around 900 thousand cycles on each page flash, if my 3 samples are in any way a valid sample pool.
Does Nordic have the distribution graph for flash fails per write-erase cycles anywhere?

 I am afraid I don't have much data on this, it's only that the endurance may be as low as 10 000 cycles as stated in the absoute maxium ratings section of the PS. And I think you should account for that number when designing your product. E.g. by allocating as many flash pages as possible to improve wear leveling. 

[dgerman]

Was this test done using high level FDS. i.e fds_record_write , fds_record_find & fds_record_open ?

Does "All subsequent reads returned an incorrect value from the flash.' mean that once a failure occures  no successful WRITES can be performed

[A.P]

Hi dgerman!
Not sure why, I wasn't able to answer you directly before, but now I am.
1. We first tested using FDS, but realized it was slowing us down, we moved to a lower level and used nrf_fstorage_read/write/erase functions.
2. All subsequent reads returned an incorrect value, yes. However, I suspect that if you happen to write a '1' to the bit that is stuck as '1', you'll get a correct value read back to you. so you've got a 50% chance to be ok ;)
3. I've added a skeletal structure of our tests in a separate comment. Hope it helps.