nRF52832 DCDC is constantly active. (Errata 63 ?)

[GoodOld]

Hi

I have 2 identical PCB just out of production - same FW - one is drawing higher current (about 600uA).

The issue is found in mass production and about 1% is having higher current.

So this is quite urgent. 

My design is based on nRF52832 product spec v1.4 Figure 170: QFAA and QFAB QFN48 with DC/DC regulator setup.

Chip marking is: N52832 QFAAE0 1927RF

Soft device is: s132_nrf52_7.0.1

SDK is: 16.0.0

When I measure with a scope on the DCC signal (pin 47) I see that the PCB with the lower current seems to switch the DCDC on and off.

On the PCB with the higher current it seems that the DCDC is running constantly.

To me it looks like the issue described in Errata 63. "POWER: DC/DC does not automatically switch off in System ON IDLE"

I have tried to use the function sd_power_dcdc_mode_set() both with enable and disable - nothing changes.

I need to know if there is a fix or workaround for this.

Thanks in advance

[GoodOld]

Correction - sd_power_dcdc_mode_set(NRF_POWER_DCDC_DISABLE); - does in fact turn the DCDC off. When I do that I measure same power consumption on both PCB.

HOWEVER ... as the overall power consumption is higher using only the LDO. This does not solve my problem.

I still need to know if there could be a fix or workaround for the issue that the DCDC in some cases does not get disabled when power consumption is low.

[hmolesworth]

I looked but don't see the threshold for auto switching from DC-DC to LDO; I wonder if there is a component tolerance issue on the DC-DC inductor and capacitor on the bad boards. A pain, but could move those components from a good board to a bad board and see if the issue moves with the components. The passive drain might mean the boards are close to the DC-DC/LDO changeover level.

Maybe also try writing to the TASKS_LOWPWR register; that is supposed to be the default, but since these registers are write-only it can't be easily checked. I don't think that would be 600uA, however.

In constant latency mode the CPU wakeup latency and the PPI task response will be constant and kept at a minimum. This is secured by forcing a set of base resources on while in sleep. The advantage of having a constant and predictable latency will be at the cost of having increased power consumption. The constant latency mode is selected by triggering the CONSTLAT task. In low power mode the automatic power management system, described in System ON mode on page 80, ensures the most efficient supply option is chosen to save the most power. The advantage of having the lowest power  possible will be at the cost of having varying CPU wakeup latency and PPI task response. The low power mode is selected by triggering the LOWPWR task. When the system enters System ON mode, it will, by default, reside in the low power sub-power mode

[GoodOld]

Thanks a lot for the answer. I think you are right, that the problem is something external to the chip. I asked the factory to take a good and a 'bad' board and switch the nRF chip on those. So the nRF chip from the good board is solderet on the 'bad' and vise-versa. After the de/re-soldering process - both boards were good ! .

So the nRF chip is not causing the problems we see. Please close this case. :-)