I have applied the errata 171 workaround to a zephyr code base with an MX25 chip and set the speed to 96MHz - when I run the application (engineering D silicon) with a scope on the QSPI clock line, I see a 2.5MHz clock. If I then change to 48MHz operation and use the alternative workaround for errata 171, I see a 42MHz clock pulse. Is it not possible to get 96MHz QSPI working on this silicon revision?
Seems that it is working, the logic analyser which was being used must not have been up to good enough a spec to capture the data, after using a different logic analyser, the clock line is correctly triggering…
Seems that it is working, the logic analyser which was being used must not have been up to good enough a spec to capture the data, after using a different logic analyser, the clock line is correctly triggering at the right speed