hi professor,
I use the zephyr spi driver to control spi nand flash.I want to send two bytes and read 3 bytes. But between write and read time sequence there are 10us delay.
As shown as the blow picture,the first 16 clocks to write, after Interval 10us 24 clocks to read.
How can I make the write and read sequence continue?
I want the clock to be continuous for read and write operations.Now The interval between write and read operations is 10us.
I did some investigation today. What I did was to read the PARTID register of the adxl362 sensor using the nRF5340. That requires a write followed by a read, like you described. It took about 9.14 us between the two transactions. I used the following code to perform the write/read at once:
static int adxl362_read_reg(uint8_t reg_addr, void *data, size_t length)
{
uint8_t access[2] = { ADXL362_READ_REG, reg_addr };
const struct spi_buf buf[2] = {
{
.buf = access,
.len = 2
},
{
.buf = data,
.len = length
}
};
struct spi_buf_set tx = {
.buffers = buf,
};
const struct spi_buf_set rx = {
.buffers = buf,
.count = 2
};
tx.count = 1;
return spi_transceive(spi_dev, &spi_cfg, &tx, &rx);
}
I triggered a GPIO when NRF_SPIM_EVENT_END happened (called END_EVENT in the image):
I also triggered a GPIO when the NRF_SPIM_TASK_START was triggered (called START_TASK in the image)
Here is the result:
As you can see, there is some delay betwwen the task NRF_SPIM_TASK_START and the begining of the transaction. This task is sent direcly to the spi, so the this delay is due to the SPI peripheral.
You can also see that there is a delay between the first transaction and the first NRF_SPIM_EVENT_END event received, that delay is also due to the SPI peripheral, since it will generate this event after the ENDRX and ENDTX events are generated, read more about it here: https://infocenter.nordicsemi.com/index.jsp?topic=%2Fps_nrf5340%2Fspim.html&cp=3_0_0_6_29_0&anchor=concept_lhv_fx2_wr
I did some investigation today. What I did was to read the PARTID register of the adxl362 sensor using the nRF5340. That requires a write followed by a read, like you described. It took about 9.14 us between the two transactions. I used the following code to perform the write/read at once:
static int adxl362_read_reg(uint8_t reg_addr, void *data, size_t length)
{
uint8_t access[2] = { ADXL362_READ_REG, reg_addr };
const struct spi_buf buf[2] = {
{
.buf = access,
.len = 2
},
{
.buf = data,
.len = length
}
};
struct spi_buf_set tx = {
.buffers = buf,
};
const struct spi_buf_set rx = {
.buffers = buf,
.count = 2
};
tx.count = 1;
return spi_transceive(spi_dev, &spi_cfg, &tx, &rx);
}
I triggered a GPIO when NRF_SPIM_EVENT_END happened (called END_EVENT in the image):
I also triggered a GPIO when the NRF_SPIM_TASK_START was triggered (called START_TASK in the image)
Here is the result:
As you can see, there is some delay betwwen the task NRF_SPIM_TASK_START and the begining of the transaction. This task is sent direcly to the spi, so the this delay is due to the SPI peripheral.
You can also see that there is a delay between the first transaction and the first NRF_SPIM_EVENT_END event received, that delay is also due to the SPI peripheral, since it will generate this event after the ENDRX and ENDTX events are generated, read more about it here: https://infocenter.nordicsemi.com/index.jsp?topic=%2Fps_nrf5340%2Fspim.html&cp=3_0_0_6_29_0&anchor=concept_lhv_fx2_wr
hi simon,
I use the nrfx SPI API but error occur in code running.What causes this error？My board type is nrf5340pdk. The same code running in 5340dk is normal.What's the difference between the two boards？
