Hello,
Is it possible to get more information on how the NWK Frame counter is stored in NVRAM. I can see fragments of code from zb_nrf52_nvram.c I see that it uses nrf_fstorage_write to strore data to nvram. If my understanding is correct, nrf_fstorage_write does not have wear leveling feature. I am using nRF5 SDK for Thread and Zigbee 4.1.0
The reason that I am asking is that I believe that there is 10000 limit on write/erase cycle on the nvram. The default data poll interval for an ED to its parent is 5 second. If each poll generate an increment of NWK counter by one. If it is persisted at the same nvram address, the address will wear out in 50000 seconds (~13 hours). I do not think this is the case as I have tested an examples that run in months so far.
Before I go to make a production run, I want to make sure that the way NWK counter is stored with some wear leveling algorithm at some level. May I have confirmation from Nordic that the flash endurance is not an issue? Please share as much information about this topic.
On separate note, I find some #define in zb_config.h such as
#if defined ZB_USE_NVRAM /** Storing NWK security counter in NVRAM */ #define ZB_STORE_COUNTERS /** Interval in which counter is stored */ #define ZB_LAZY_COUNTER_INTERVAL 0x400 #endif /*ZB_USE_NVRAM*/
I am assuming these are for information only. Am I correct? The interesting number is ZB_LAZY_COUNTER_INTERVAL value. What does it mean? a hex 0x400 is 1024 Does the counter write is delayed for 1024 millisecond to prevent extreme high frequency of nwk write? Even at these type of interval and 10000 write/erase cycle limit, we do not go very long if there is no wear leveling.
Thank you in advance for your time and attention. I am looking forward to your answer.
br
Iman
