nRF905 Tx to Rx Delay and Jitter

[David Murray]

We are considering useing this chip for a short range link. We want to use a synch character at the start of the transmitted message to accurately synchronise a process at the receiver. What is the delay between the start of the TX char being clocked into the SPI and the start of the RX char being clocked out of the SPI. More importantly what is the variability (jitter) in this delay. Assume that there has been a signifcant delay since the last character so that all buffers are clear. Also assume that the transmitter and receiver are fully powered up.

[Jon Gunnar]

I think you have misunderstood the way the nRF905 works. The data you clock in on the TX SPI as a packet payload will be buffered inside the radio until you initiate the transmission by pulling TRX_CE high. On the RX end, you will be notified by the DR (data ready) signal when a valid packet is received completely.

The time it takes from you pull TRX_CE high on the TX side until you get a DR on the RX side is dependent on your packet length since the whole packet has to be received by the RX before you get DR high. Chapter 10 in the nRF905 Product Specification gives you the details on how to calculate this. For a packet with 4 bytes address, 1 byte CRC and 1 byte payload, the time is 650us + 200 us + ((4+1+1)*8)/50000b/s =1810us. The variation of this time can be as high as +/-20us.